公开(公告)号：WO2012082092A1

公开(公告)日：2012-06-21

申请号：PCT/US2010/059996

申请日：2010-12-13

Applicant: ARM LIMITED ,  MCLAURIN, Teresa, Louise

Inventor： MCLAURIN, Teresa, Louise

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/50 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is formed of a plurality of circuit dies 22, 24 having through silicon vias (TSVs) passing there-through. The placement patterns of the through silicon vias differ between the circuit dies. An inter-die routing layer is provided either in a face of a substrate of one of the circuit dies or in an outer face of a layer of processing circuitry of one of the circuit dies. The inter-die routing layer bridges the gaps between the vias and the connection points of different circuit dies. The inter-die routing layer may be formed of metal tracks.

Abstract translation: 集成电路由具有通过硅通孔（TSV）的多个电路管芯22,24形成。 通孔硅通孔的布置图案在电路管芯之间不同。 芯片间路由层被提供在电路管芯之一的衬底的表面或电路管芯之一的处理电路层的外表面中。 管芯间布线层桥接了通孔和不同电路管芯的连接点之间的间隙。 芯片间布线层可以由金属轨道形成。