公开(公告)号：WO2013063450A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/062195

申请日：2012-10-26

Applicant: LSI CORPORATION ,  AZADET, Kameran ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  YU, Meng-lin ,  SANCHEZ, Ramon

Inventor： AZADET, Kameran ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  YU, Meng-lin ,  SANCHEZ, Ramon

IPC: H04L25/02

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.

Abstract translation: 提供了基于块的波峰因数降低（CFR）技术。 一种示例性的基于块的波峰因子降低方法包括获得由多个样本组成的数据样本块; 将数据块应用于波峰因数减少块; 并从波峰因数减小块提供经处理的数据块。 可以可选地对块数据迭代地执行基于块的波峰因数降低方法。 数据样本块可以包括具有至少一个光标块的扩展块。 例如，可以使用至少两个前置光标块和一个后置光标块。 可以例如仅在数据样本块和第一个前缀块中取消峰值。

公开(公告)号：WO2017167354A1

公开(公告)日：2017-10-05

申请号：PCT/EP2016/056810

申请日：2016-03-29

Applicant: INTEL CORPORATION ,  MOLINA, Albert ,  AZADET, Kamran

Inventor： MOLINA, Albert ,  AZADET, Kamran

IPC: H03F1/32 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F1/3247 ,  H03F1/3258 ,  H03F3/195 ,  H03F3/245 ,  H03F2200/111 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233

Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

Abstract translation: 信号处理电路装置可以包括前置放大器电路，其被配置为将第一维度输入和第二维度输入映射到二维（2D）查找的多个查找表系数的第一子集 表，其中所述第一维度输入和所述第二维度输入各自表示一个或多个输入信号的信号电平，从所述多个查找表系数的所述第一子集外推以生成查找表输出，并且将所述查找表输出应用于 该一个或多个输入信号为放大器生成预失真的输入信号。

公开(公告)号：WO2013066756A3

公开(公告)日：2013-08-15

申请号：PCT/US2012062179

申请日：2012-10-26

Applicant: LSI CORP ,  AZADET KAMERAN ,  LI CHENGZHOU ,  MOLINA ALBERT ,  OTHMER JOSEPH H ,  PINAULT STEVEN C ,  YU MENG-LIN ,  WILLIAMS JOSEPH ,  PEREZ RAMON SANCHEZ ,  CHEN JIAN-GUO

Inventor： AZADET KAMERAN ,  LI CHENGZHOU ,  MOLINA ALBERT ,  OTHMER JOSEPH H ,  PINAULT STEVEN C ,  YU MENG-LIN ,  WILLIAMS JOSEPH ,  PEREZ RAMON SANCHEZ ,  CHEN JIAN-GUO

IPC: H04L25/03

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max() instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt() instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract translation: 提供软件数字前端（SoftDFE）信号处理技术。 通过在处理器上执行一个或多个专用指令对信号执行一个或多个数字前端（DFE）功能，对软件中的信号执行一个或多个数字前端（DFE）功能，其中处理器具有指令 由线性和非线性指令中的一个或多个组成。 可选地形成由多个数据样本组成的样本块，并且在样本块上执行数字前端（DFE）功能。 专门的指令可以包括向量卷积函数，复指数函数，xk函数，向量比较指令，向量max（）指令，向量乘法指令，向量加法指令，向量sqrt（）指令，向量 1 / x指令和用户定义的非线性指令。

公开(公告)号：WO2013063447A2

公开(公告)日：2013-05-02

申请号：PCT/US2012062191

申请日：2012-10-26

Applicant: LSI CORP ,  AZADET KAMERAN ,  MOLINA ALBERT ,  OTHMER JOSEPH H ,  VENKATARAGHAVAN PARAKALAN ,  YU MENG-LIN ,  WILLIAMS JOSEPH

Inventor： AZADET KAMERAN ,  MOLINA ALBERT ,  OTHMER JOSEPH H ,  VENKATARAGHAVAN PARAKALAN ,  YU MENG-LIN ,  WILLIAMS JOSEPH

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to theta; and computing a fine corrective value using a polynomial approximation.

Abstract translation: 数字处理器提供具有复指数函数的指令集。 数字处理器通过获得具有输入值x的复指数软件指令作为输入来评估输入值x的复指数函数; 并且响应于所述复指数软件指令：调用至少一个复指数函数单元，所述指数函数单元实现复指数软件指令以将所述复指数函数应用于所述输入值x; 并生成对应于输入值x的复指数的输出。 输入值x的复指数函数可以通过包装输入值以保持给定范围来评估; 使用查找表来计算粗略的近似角; 缩放粗略近似角以获得从0到θ的角度; 并使用多项式近似来计算精确的校正值。

公开(公告)号：WO2013063443A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/062186

申请日：2012-10-26

Applicant: LSI CORPORATION ,  AZADET, Kameran ,  YU, Meng-Lin ,  PINAULT, Steven, C. ,  WILLIAMS, Joseph ,  MOLINA, Albert

Inventor： AZADET, Kameran ,  YU, Meng-Lin ,  PINAULT, Steven, C. ,  WILLIAMS, Joseph ,  MOLINA, Albert

IPC: H04L25/02

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A processor is provided having an instruction set with user-defined non-linear functions for digital pre-distortion (DPD) and other non-linear applications. A signal processing function, such as DPD, is implemented in software by obtaining at least one software instruction that performs at least one non-linear function for an input value, x, wherein the at least one non-linear function comprises at least one user-specified parameter; in response to at least one of the software instructions for at least one non-linear function having at least one user-specified parameter, performing the following steps: invoking at least one functional unit that implements the at least one software instruction to apply the non-linear function to the input value, x; and generating an output corresponding to the non-linear function for the input value, x. The user-specified parameter can optionally be loaded from memory into at least one register.

Abstract translation: 提供了具有用于数字预失真（DPD）和其他非线性应用的用户定义的非线性函数的指令集的处理器。 诸如DPD的信号处理功能通过获得对输入值x执行至少一个非线性函数的至少一个软件指令来在软件中实现，其中至少一个非线性函数包括至少一个用户 指定参数; 响应于至少一个具有至少一个用户指定参数的非线性函数的软件指令中的至少一个，执行以下步骤：调用实现所述至少一个软件指令的至少一个功能单元， 线性函数到输入值x; 并且生成对应于输入值x的非线性函数的输出。 用户指定的参数可以可选地从存储器加载到至少一个寄存器中。

公开(公告)号：WO2018119153A2

公开(公告)日：2018-06-28

申请号：PCT/US2017/067739

申请日：2017-12-20

Applicant: INTEL CORPORATION ,  INTEL IP CORPORATION ,  ALPMAN, Erkan ,  AMADJIKPE, Arnaud Lucres ,  OSAF, Omer ,  AZADET, Kameran ,  BANIN, Rotem ,  BARYAKH, Miroslav ,  BAZOV, Anat ,  BRENNA, Stefano ,  CASPER, Bryan K. ,  CHAKRABARTI, Anandaroop ,  CHANCE, Gregory ,  CHOUDHURY, Debabani ,  COHEN, Emanuel ,  DA SILVA, Claudio ,  DALMIA, Sidharth ,  DANESHGAR ASL, Saeid ,  DASGUPTA, Kaushik ,  DATTA, Kunal ,  DAVIS, Brandon ,  DEGANI, Ofir ,  FAHIM, Amr M. ,  FREIMAN, Amit ,  GENOSSAR, Michael ,  GERSON, Eran ,  GOLDBERGER, Eyal ,  GORDON, Eshel ,  GORDON, Meir ,  HAGN, Josef ,  KANG, Shinwon ,  KAO, Te Yu ,  KOGAN, Noam ,  KOMULAINEN, Mikko S. ,  KUSHNIR, Igal Yehuda ,  LAHTI, Saku ,  LAMPINEN, Mikko M. ,  LANDSBERG, Naftali ,  LEE, Wook Bong ,  LEVINGER, Run ,  MOLINA, Albert ,  MONTOYA MORENO, Resti ,  MUSAH, Tawfiq ,  NAREVSKY, Nathan G. ,  NIKOPOUR, Hosein ,  ORHAN, Oner ,  PALASKAS, Georgios ,  PELLERANO, Stefano ,  PONGRATZ, Ron ,  RAVI, Ashoke ,  RAVID, Shmuel ,  SAGAZIO, Peter Andrew ,  SASOGLU, Eren ,  SHAKEDD, Lior ,  SHOR, Gadi ,  SINGH, Baljit ,  SOFFER, Menashe ,  SOVER, Ra'anan ,  TALWAR, Shilpa ,  TANZI, Nebil ,  TEPLITSKY, Moshe ,  THAKKAR, Chintan S. ,  THAKUR, Jayprakash ,  TSARFATI, Avi ,  TSFATI, Yossi ,  VERHELST, Marian ,  WEISMAN, Nir ,  YAMADA, Shuhei ,  YEPES, Ana M. ,  KITCHIN, Duncan

Inventor： ALPMAN, Erkan ,  AMADJIKPE, Arnaud Lucres ,  OSAF, Omer ,  AZADET, Kameran ,  BANIN, Rotem ,  BARYAKH, Miroslav ,  BAZOV, Anat ,  BRENNA, Stefano ,  CASPER, Bryan K. ,  CHAKRABARTI, Anandaroop ,  CHANCE, Gregory ,  CHOUDHURY, Debabani ,  COHEN, Emanuel ,  DA SILVA, Claudio ,  DALMIA, Sidharth ,  DANESHGAR ASL, Saeid ,  DASGUPTA, Kaushik ,  DATTA, Kunal ,  DAVIS, Brandon ,  DEGANI, Ofir ,  FAHIM, Amr M. ,  FREIMAN, Amit ,  GENOSSAR, Michael ,  GERSON, Eran ,  GOLDBERGER, Eyal ,  GORDON, Eshel ,  GORDON, Meir ,  HAGN, Josef ,  KANG, Shinwon ,  KAO, Te Yu ,  KOGAN, Noam ,  KOMULAINEN, Mikko S. ,  KUSHNIR, Igal Yehuda ,  LAHTI, Saku ,  LAMPINEN, Mikko M. ,  LANDSBERG, Naftali ,  LEE, Wook Bong ,  LEVINGER, Run ,  MOLINA, Albert ,  MONTOYA MORENO, Resti ,  MUSAH, Tawfiq ,  NAREVSKY, Nathan G. ,  NIKOPOUR, Hosein ,  ORHAN, Oner ,  PALASKAS, Georgios ,  PELLERANO, Stefano ,  PONGRATZ, Ron ,  RAVI, Ashoke ,  RAVID, Shmuel ,  SAGAZIO, Peter Andrew ,  SASOGLU, Eren ,  SHAKEDD, Lior ,  SHOR, Gadi ,  SINGH, Baljit ,  SOFFER, Menashe ,  SOVER, Ra'anan ,  TALWAR, Shilpa ,  TANZI, Nebil ,  TEPLITSKY, Moshe ,  THAKKAR, Chintan S. ,  THAKUR, Jayprakash ,  TSARFATI, Avi ,  TSFATI, Yossi ,  VERHELST, Marian ,  WEISMAN, Nir ,  YAMADA, Shuhei ,  YEPES, Ana M. ,  KITCHIN, Duncan

Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

公开(公告)号：WO2013063440A1

公开(公告)日：2013-05-02

申请号：PCT/US2012/062182

申请日：2012-10-26

Applicant: LSI CORPORATION ,  AZADET, Kameran ,  YU, Meng-lin ,  OTHMER, Joseph, H. ,  WILLIAMS, Joseph ,  MOLINA, Albert

Inventor： AZADET, Kameran ,  YU, Meng-lin ,  OTHMER, Joseph, H. ,  WILLIAMS, Joseph ,  MOLINA, Albert

IPC: G06F17/16 ,  G06F9/06

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises N1 samples; and performing a weighted sum of the time shifted versions of the vector by a vector of N1 coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract translation: 提供了具有矢量卷积函数的指令集的向量处理器。 所公开的向量处理器通过获得包括至少N1 + N2-1个输入样本的向量来执行输入信号和滤波器脉冲响应之间的卷积函数; 获得矢量的N2时移版本（包括零位版本），其中每个时移版本包括N1个样本; 以及通过N1系数的向量来执行向量的时移版本的加权和; 以及产生包括每个加权和的一个输出值的输出向量。 矢量处理器例如响应于具有矢量输入的一个或多个矢量卷积软件指令来执行该方法。 矢量可以包括多个实数或复数输入样本，并且可以使用实数或复数的多个系数来表示滤波器脉冲响应。

公开(公告)号：WO2013066756A2

公开(公告)日：2013-05-10

申请号：PCT/US2012/062179

申请日：2012-10-26

Applicant: LSI CORPORATION ,  AZADET, Kameran ,  LI, Chengzhou ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  PINAULT, Steven, C. ,  YU, Meng-Lin ,  WILLIAMS, Joseph ,  PEREZ, Ramon, Sanchez ,  CHEN, Jian-Guo

Inventor： AZADET, Kameran ,  LI, Chengzhou ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  PINAULT, Steven, C. ,  YU, Meng-Lin ,  WILLIAMS, Joseph ,  PEREZ, Ramon, Sanchez ,  CHEN, Jian-Guo

CPC classification number: G06F9/3001 ,  G06F5/01 ,  G06F9/30036 ,  G06F17/15 ,  H03F1/0288 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H03H17/06 ,  H03M3/30 ,  H04B1/0003 ,  H04B1/0475 ,  H04B1/62 ,  H04B2001/0408 ,  H04L1/0054 ,  H04L25/02 ,  H04L25/03 ,  H04L25/03178 ,  H04L25/03216 ,  H04L25/4917 ,  H04L27/2334

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an x k function, a vector compare instruction, a vector max() instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt() instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract translation: 提供了软件数字前端（SoftDFE）信号处理技术。 通过在处理器上执行一个或多个专用指令来对信号执行一个或多个数字前端（DFE）功能，以对信号执行一个或多个数字前端（DFE）功能，其中处理器具有指令 由一个或多个线性和非线性指令组成。 可选地形成由多个数据样本组成的样本块，并且在该样本块上执行数字前端（DFE）功能。 专用指令可以包括矢量卷积函数，复指数函数，xk函数，矢量比较指令，矢量max（）指令，矢量乘法指令，矢量加法指令， 矢量sqrt（）指令，矢量1 / x指令和用户定义的非线性指令。

公开(公告)号：WO2013063447A3

公开(公告)日：2013-05-02

申请号：PCT/US2012/062191

申请日：2012-10-26

Applicant: LSI CORPORATION ,  AZADET, Kameran ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  VENKATARAGHAVAN, Parakalan ,  YU, Meng-lin ,  WILLIAMS, Joseph

Inventor： AZADET, Kameran ,  MOLINA, Albert ,  OTHMER, Joseph, H. ,  VENKATARAGHAVAN, Parakalan ,  YU, Meng-lin ,  WILLIAMS, Joseph

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to θ; and computing a fine corrective value using a polynomial approximation.