公开(公告)号：WO2012038338A1

公开(公告)日：2012-03-29

申请号：PCT/EP2011/066101

申请日：2011-09-16

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MU, Fenghao ,  WILHELMSSON, Leif ,  SUNDSTRÖM, Lars

Inventor： MU, Fenghao ,  WILHELMSSON, Leif ,  SUNDSTRÖM, Lars

IPC: H03D7/16 ,  H03D7/18

CPC classification number: H04L27/389 ,  H03D7/166 ,  H03D2200/0088 ,  H04B1/126 ,  H04L25/08

Abstract: A complex intermediate frequency mixer (IFM) for frequency translating a received complex intermediate frequency, IF, signal, wherein the received complex IF signal comprises at least two frequency bands located at upper-side and lower-side of 0Hz, is provided. The complex intermediate frequency mixer comprises a first, second, third and fourth mixer (M1, M2, M3, M4). The complex intermediate frequency mixer further comprises a first, second, third and fourth gain adjusting component (α1, α2, δ2, δ1), connected to a first, second, third and fourth mixer output (M1-out, M2-out, M3-out, M4-out), respectively. Moreover, a first summing unit (S1), connected to a first gain output (α1-out), a fourth gain output (δ1-out) and a third mixer output (M3-out) negated, and second summing unit (S2), connected to the second gain output (α2-out), the third gain output (δ2-out) and the fourth mixer output (M4-out), are configured to output a first baseband complex signal of the received complex IF signal.

Abstract translation: 一种用于频率转换接收的复合中频IF（IF）信号的复合中频混频器（IFM），其中接收到的复合IF信号包括位于0Hz的上侧和下侧的至少两个频带。 复合中频混频器包括第一，第二，第三和第四混频器（M1，M2，M3，M4）。 复合中频混频器还包括连接到第一，第二，第三和第四混频器输出（M1-out，M2-out，M3）的第一，第二，第三和第四增益调整组件（a1，a2，d2，d1） -out，M4-out）。 此外，连接到第一增益输出（a1-out），第四增益输出（d1-out）和第三混频器输出（M3-out）的第一求和单元（S1）被否定，以及第二加法单元（S2） ，连接到第二增益输出（a2-out），第三增益输出（d2-out）和第四混频器输出（M4-out），被配置为输出接收到的复合IF信号的第一基带复信号。

公开(公告)号：WO2009130207A3

公开(公告)日：2010-06-10

申请号：PCT/EP2009054723

申请日：2009-04-21

Applicant: ERICSSON TELEFON AB L M ,  MU FENGHAO ,  TILLMAN FREDRIK

Inventor： MU FENGHAO ,  TILLMAN FREDRIK

IPC: H03D7/14 ,  H03D7/16

CPC classification number: H03D7/166 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1466 ,  H03D7/163 ,  H03D7/165 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03D2200/0088 ,  H03D2200/009

Abstract: According to one embodiment, a radio frequency receiver includes a quadrature mixer for converting radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer includes an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer includes a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a first set of clock signals and a second set of clock signals. The first set of clock signals has a frequency twice that of the second set of clock signals. The first set of clock signals is arranged to drive the mixer input switch transistors and the second set of clock signals is arranged to drive the output switch transistors.

Abstract translation: 根据一个实施例，射频接收机包括用于将射频信号转换成基带信号或中频信号的正交混频器。 正交混频器包括同相无源混频器和正交相位无源混频器。 每个无源混频器包括具有多个混频器输入开关晶体管的混频器核心和连接到混频器输入开关晶体管的多个输出开关晶体管。 时钟电路产生第一组时钟信号和第二组时钟信号。 第一组时钟信号的频率是第二组时钟信号的两倍。 第一组时钟信号被布置成驱动混频器输入开关晶体管，并且第二组时钟信号被布置成驱动输出开关晶体管。

公开(公告)号：WO2009130209A3

公开(公告)日：2009-10-29

申请号：PCT/EP2009/054725

申请日：2009-04-21

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MU, Fenghao ,  TILLMAN, Fredrik

Inventor： MU, Fenghao ,  TILLMAN, Fredrik

IPC: H03D7/14 ,  H03D7/16

Abstract: According to one embodiment, a radio frequency receiver comprises a quadrature mixer configured to convert radio frequency signals to baseband signals or intermediate frequency signals. The quadrature mixer comprises an in-phase passive mixer and a quadrature-phase passive mixer. Each passive mixer comprises a mixer core having a plurality of mixer input switch transistors and a plurality of output switch transistors connected to the mixer input switch transistors. Clock circuitry generates a plurality of quadrature pulsed clock signals and delayed versions of the quadrature pulsed clock signals. The quadrature pulsed clock signals and the delayed versions of the quadrature pulsed clock signals drive the mixer input switch transistors and the output switch transistors.

公开(公告)号：WO2011101289A1

公开(公告)日：2011-08-25

申请号：PCT/EP2011/052006

申请日：2011-02-11

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MU, Fenghao

Inventor： MU, Fenghao

IPC: H03D7/18 ,  H04L25/03 ,  H04B1/69 ,  H04B1/707

CPC classification number: H03D7/166

Abstract: A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up- converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal. The second clock driver/divider further amplifies and clips the compensated version of first-clipped clock signal to generate the wanted RF clock signal.

Abstract translation: 时钟发生器电路通过使用上变频器，伪噪声消除电路，控制器和至少两个时钟驱动器/分频器来产生所需的RF时钟信号。 伪噪声消除电路包括音调检测电路和音调产生电路。 上变频器将调制信号与本地正交RF时钟信号混合，以产生具有等于所需RF时钟信号的期望频率的频率音调的上变频信号。 第一个时钟驱动器/分频器放大并将上变频信号剪辑成第一个削波的时钟信号。 音调检测电路检测基带域中的第一限幅时钟信号的不需要的音调的幅度和相位，并向控制器提供信息，该控制器控制音调发生电路以消除不想要的音调并创建第一限幅时钟 时钟信号。 第二个时钟驱动器/分频器进一步放大和钳位补偿版本的第一个削波时钟信号，以产生所需的RF时钟信号。

公开(公告)号：WO2011015534A2

公开(公告)日：2011-02-10

申请号：PCT/EP2010/061137

申请日：2010-07-30

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (publ) ,  MU, Fenghao

Inventor： MU, Fenghao

IPC: H03C3/40

CPC classification number: H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0025 ,  H03D2200/0084 ,  H03D2200/009

Abstract: A differential positive coefficient weighted quadrature modulator is actuated responsive to quadrature clock signals and positive digital modulation signals input to the modulator. The modulator includes an l-channel positive coefficient weighted modulator (PCWM) and a Q-channel PCWM. The l-channel PCWM has differential output nodes configured to output a differential l-channel signal responsive to the state of first and second positive digital modulation signals and first and second complimentary quadrature clock signals input to the l-channel PCWM. The Q-channel PCWM has differential output nodes configured to output a differential Q-channel signal responsive to the state of third and fourth positive digital modulation signals and third and fourth complimentary quadrature clock signals input to the Q-channel PCWM. The positive digital modulation signals input to the l-channel and Q-channel PCWMs have positive amplitude and the l-channel and Q-channel PCWMs conduct at approximately half clock cycle or less of the corresponding quadrature clock signals.

Abstract translation: 响应于输入到调制器的正交时钟信号和正数字调制信号，启动差分正系数加权正交调制器。 调制器包括1通道正系数加权调制器（PCWM）和Q通道PCWM。 1通道PCWM具有差分输出节点，其被配置为响应于第一和第二正数字调制信号的状态以及输入到1通道PCWM的第一和第二互补正交时钟信号来输出差分1通道信号。 Q通道PCWM具有差分输出节点，其被配置为响应于输入到Q信道PCWM的第三和第四正数字调制信号的状态以及输入到Q信道PCWM的第三和第四互补正交时钟信号来输出差分Q信道信号。 输入到1信道和Q信道PCWM的正数字调制信号具有正振幅，并且1信道和Q信道PCWM在相应的正交时钟信号的大约半个时钟周期或更短周期内传导。

公开(公告)号：WO2009106515A1

公开(公告)日：2009-09-03

申请号：PCT/EP2009/052147

申请日：2009-02-24

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MU, Fenghao

Inventor： MU, Fenghao

IPC: H04B1/12 ,  H04B1/52

CPC classification number: H04B1/525 ,  H03F1/02 ,  H03F3/24 ,  H04B1/123 ,  H04B1/126 ,  H04B2001/045

Abstract: Active transmitter leakage cancellation techniques are disclosed, for reducing transmitter leakage in a frequency-duplexing radio transceiver. Reducing transmitter leakage to the receiver path of a duplex transceiver eases the linearity requirements for low-noise amplifier and mixer circuits, potentially reducing transceiver cost as well as complexity. In an exemplary method, a radio-frequency (RF) cancellation signal is generated from a transmitter signal, and the RF cancellation signal is combined with a received RF signal to obtain a combined RF signal comprising a residual transmitter leakage component. The residual transmitter leakage component of the combined RF signal is converted, using, e.g., a frequency mixer, to obtain a down-converted signal at baseband or at an intermediate frequency. A magnitude of the residual transmitter leakage component is detected from the down-converted signal, and used to adjust the phase or amplitude of the RF cancellation signal, or both, to reduce the residual transmitter leakage component.

Abstract translation: 公开了主动发射机泄漏消除技术，用于减少频率双工无线电收发器中的发射机泄漏。 将发射机泄漏减少到双工收发器的接收器路径可以降低低噪声放大器和混频器电路的线性要求，从而可能降低收发器成本以及复杂性。 在示例性方法中，从发射机信号产生射频（RF）消除信号，并且将RF消除信号与接收的RF信号组合以获得包括残余发射机泄漏分量的组合RF信号。 组合的RF信号的残余发射机泄漏分量使用例如混频器进行转换，以在基带或中频获得下变频信号。 从下变频信号中检测残留发射机泄漏分量的大小，并用于调整RF消除信号或两者的相位或幅度，以减少残余发射机泄漏分量。

公开(公告)号：WO2008145604A1

公开(公告)日：2008-12-04

申请号：PCT/EP2008/056353

申请日：2008-05-23

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ,  MU, Fenghao

Inventor： MU, Fenghao

IPC: H03F1/26 ,  H03F1/52 ,  H03F3/191 ,  H03F3/72 ,  H03G3/20 ,  H03G3/30 ,  H03F1/30 ,  H03F1/22 ,  H03F1/56

CPC classification number: H03F1/26 ,  H03F1/223 ,  H03F1/30 ,  H03F1/52 ,  H03F1/56 ,  H03F3/191 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/372 ,  H03F2200/429 ,  H03F2200/447 ,  H03F2200/456 ,  H03F2200/489 ,  H03F2200/492 ,  H03F2203/7206 ,  H03F2203/7209 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A configurable LNA architecture for a multi-band RF receiver front end (10) comprises a bank of LNAs, (12) each optimized to a different frequency band, wherein each LNA (12) has a configurable topology. Each LNA (12) comprises a plurality of amplifier stages, each stage including an RF transistor having a different width. The transistor widths in adjacent amplifier stages may be binary weighted, or may be sized to achieve a constant gain step. By selectively enabling and disabling RF transistors, the effective transistor width of the LNA (12) can be controlled with a fine granularity. A DAC generates a bias voltage with a small quantization step, additionally providing a fine granularity of gain control. The LNAs (12) are protected by overvoltage protection circuits which shield transistors from a supply voltage in excess of their breakdown voltage. A source degeneration inductor (L5) presents a real resistance at inputs of the LNAs (L5), without introducing thermal noise.

Abstract translation: 用于多频带RF接收机前端（10）的可配置LNA架构包括每一个优化为不同频带的LNA组（12），其中每个LNA（12）具有可配置拓扑。 每个LNA（12）包括多个放大器级，每个级包括具有不同宽度的RF晶体管。 相邻放大器级中的晶体管宽度可以是二进制加权的，或者可以被设计成实现恒定的增益步长。 通过选择性地启用和禁用RF晶体管，可以以细粒度控制LNA（12）的有效晶体管宽度。 DAC产生具有小量化步长的偏置电压，另外提供细微的增益控制粒度。 LNA（12）由过电压保护电路保护，该电路将晶体管屏蔽超过其击穿电压的电源电压。 源变性电感（L5）在LNA（L5）的输入端呈现实际电阻，而不引入热噪声。

公开(公告)号：WO2012074460A1

公开(公告)日：2012-06-07

申请号：PCT/SE2011/051423

申请日：2011-11-24

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MU, Fenghao

Inventor： MU, Fenghao

IPC: H03H7/42 ,  H04B1/18 ,  H01F21/12

CPC classification number: H03H7/42 ,  H03H7/0153 ,  H03H7/06 ,  H03H7/1775 ,  H03H2250/00

Abstract: A circuit converts a single-ended signal to differential signals that are balanced to have the same amplitudes and opposite phases. The circuit includes a balance tunable balun, a detector, and a controller. The balance tunable balun has a primary winding, a secondary winding, a control input, and a switched resistor-capacitor (RC) network. The primary winding receives the single-ended signal and the secondary winding outputs the differential signals. The control input receives a control signal and the switched RC network tunes an output imbalance of the balun responsive to this control signal. The detector detects the output imbalance and the controller generates the control signal to control the switched RC network to reduce that output imbalance. The circuit produces well balanced differential signals over a wide range of signal frequencies,even when asymmetries, process variations, or parasitic capacitance in the balun would otherwise result in imbalance.

Abstract translation: 电路将单端信号转换为平衡的具有相同幅度和相位相位的差分信号。 电路包括平衡可调平衡 - 不平衡转换器，检测器和控制器。 平衡可调平衡不平衡转换器具有初级绕组，次级绕组，控制输入和开关电阻 - 电容（RC）网络。 初级绕组接收单端信号，次级绕组输出差分信号。 控制输入​​接收控制信号，并且交换的RC网络响应于该控制信号来调谐平衡 - 不平衡变换器的输出不平衡。 检测器检测输出不平衡，并且控制器产生控制信号以控制切换的RC网络，以减少输出不平衡。 即使在不平衡变压器中的非对称性，工艺变化或寄生电容导致不平衡的情况下，该电路也可在宽范围的信号频率上产生良好平衡的差分信号。

公开(公告)号：WO2011054727A1

公开(公告)日：2011-05-12

申请号：PCT/EP2010/066365

申请日：2010-10-28

Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL) ,  MATTISSON, Sven ,  MU, Fenghao

Inventor： MATTISSON, Sven ,  MU, Fenghao

IPC: H03F3/24 ,  H03F3/195 ,  H04L27/36 ,  H03F3/21 ,  H03C5/00 ,  H04L27/20

CPC classification number: H03F3/24 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/336

Abstract: A digital affine transformation modulator and power amplifier drives a transmitter antenna. The modulator performs an affine transformation on a signal, wherein the I, Q space is mapped to a plurality of sectors. A signal in a sector is expressed as the sum of two vectors, the angles of which define the sector boundaries. A digital power amplifier comprises a plurality of amplifier cells, each cell comprising at least two amplifier units. For a given signal, each amplifier unit selectively amplifies a clock signal having a phase corresponding to one of the boundary angles of the signal's affine transformed sector. A subset of the plurality of amplifier cells receiving each phase clock signal are enabled, based on the magnitude of the associated vector describing the signal in affine transform space. The modulation scheme exhibits higher efficiency than quadrature modulation, without the bandwidth expansion and group delay mismatch of polar modulation.

Abstract translation: 数字仿射变换调制器和功率放大器驱动发射机天线。 调制器对信号执行仿射变换，其中I，Q空间映射到多个扇区。 扇区中的信号被表示为两个矢量的和，它们的角度限定了扇区边界。 数字功率放大器包括多个放大器单元，每个单元包括至少两个放大器单元。 对于给定信号，每个放大器单元选择性地放大具有对应于信号仿射变换扇区的一个边界角的相位的时钟信号。 基于描述仿射变换空间中的信号的相关矢量的大小，启用接收每个相位时钟信号的多个放大器单元的子集。 调制方案表现出比正交调制更高的效率，没有频带扩展和极化调制的群延迟失配。

公开(公告)号：WO2010115723A3

公开(公告)日：2010-12-09

申请号：PCT/EP2010053910

申请日：2010-03-25

Applicant: ERICSSON TELEFON AB L M ,  MU FENGHAO

Inventor： MU FENGHAO

IPC: H03J1/00 ,  H03J3/20

CPC classification number: H03J3/20 ,  H03J2200/10 ,  H04B1/18

Abstract: A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode.

Abstract translation: 描述了包括电感器和可变电容器的LC谐振电路的调谐方法和电路。 在调谐模式中，将RF输入信号施加到电路的输入端口，并且随着可变电容器控制输入变化而监视RF输出信号。 检测到峰值输出，并且存储相应的可变电容器控制输入，并且在工作模式下将其施加到可变电容器。 在一个实施例中，可变电容器控制输入被调整用于峰值检测过程中的延迟。 在一个实施例中，可变电容器包括粗电容器和精细电容器; 对每个电容器重复调谐过程; 并且粗略和精细的可变电容器控制输入被存储并且在操作模式下被施加到相应的电容器。