LOW-NOISE AMPLIFIER (LNA) INPUT IMPEDANCE ADJUSTMENT CIRCUIT

    公开(公告)号:WO2023076179A1

    公开(公告)日:2023-05-04

    申请号:PCT/US2022/047598

    申请日:2022-10-24

    IPC分类号: H03F1/22 H03F1/34 H03F3/195

    摘要: Aspects of the present disclosure provide a circuit (810) configured to adjust an input impedance of an amplifier such as a low-noise amplifier (130). In certain aspects, the circuit (810) is coupled to a node (X), wherein the node (X) is between a first transistor (410) and a second transistor (420) of the amplifier (130). The circuit may include an inductor (Lf) and a capacitor (Cf) coupled in series, wherein the inductor (Lf) is coupled with one or more load inductors (Ld) of the amplifier (130) through negative magnetic coupling (M).

    WIDEBAND AMPLIFIER TUNING
    4.
    发明申请

    公开(公告)号:WO2022056150A1

    公开(公告)日:2022-03-17

    申请号:PCT/US2021/049698

    申请日:2021-09-09

    申请人: PSEMI CORPORATION

    摘要: Circuit and methods using a single low-noise amplifier (LNA) to provide amplification for a wide band of RF frequencies while maintaining high gain and a low noise factor. Embodiments include an amplifier circuit including an input signal path for receiving a wideband RF signal; a switched inductor tuning block coupled to the input signal path and configured to selectively couple one of a plurality of inductances to the input signal path; and an amplifier coupled to the switched inductor tuning block and configured to receive the RF signal after passage through the selected coupled inductance. The switched inductor tuning block includes a plurality of selectable branches, each including an RF input switch; an RF output switch; an inductor coupled between the RF input switch and the RF output switch; and first and second shunt switches coupled between a respective terminal of the inductor and circuit ground.

    増幅回路
    5.
    发明申请
    増幅回路 审中-公开

    公开(公告)号:WO2021117375A1

    公开(公告)日:2021-06-17

    申请号:PCT/JP2020/040983

    申请日:2020-10-30

    发明人: 杉山 幸大

    摘要: 増幅回路(100)は、入力端子(t1)と出力端子(t2)との間に設けられた第1増幅器(10)と、入力端子(t1)と出力端子(t2)との間で第1増幅器(10)と並列接続された第2増幅器(20)と、を備え、第1増幅器(10)は、カスコード接続されたトランジスタ(M1)およびトランジスタ(M2)を含み、第2増幅器(20)は、トランジスタ(M3)を含み、トランジスタ(M1)は、入力端子(t1)に接続されたゲート、グランドに接続されたソース、および、ドレインを有し、トランジスタ(M2)は、ゲート、トランジスタ(M1)のドレインに接続されたソース、および、出力端子(t2)に接続されたドレインを有し、トランジスタ(M3)は、入力端子(t1)に接続されたゲート、グランドに接続されたソース、および、出力端子(t2)に接続されたドレインを有する。

    AMPLIFIER INPUT PROTECTION CIRCUITS
    6.
    发明申请

    公开(公告)号:WO2020163708A1

    公开(公告)日:2020-08-13

    申请号:PCT/US2020/017200

    申请日:2020-02-07

    摘要: Amplifier input protection circuits are described. In one embodiment, a photoreceiver for a lidar system has a photodetector configured to generate an output current in response to received light. A transimpedance amplifier is configured to receive the output current and generate a voltage output corresponding to the output current in response thereto, and a diode circuit has a cathode coupled at a node between the photodetector output and the transimpedance amplifier input.

    APPARATUS FOR OPTIMIZED TURN-OFF OF A CASCODE AMPLIFIER

    公开(公告)号:WO2020144554A1

    公开(公告)日:2020-07-16

    申请号:PCT/IB2020/050056

    申请日:2020-01-06

    IPC分类号: H03F1/22 H03F1/02 H03F1/30

    摘要: An apparatus for turning off a cascode amplifier having a common-gate transistor and a common-source transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a drain-voltage from the drain of the common-source transistor when the common-source transistor is switched to a first OFF state and produce a first feedback signal. The drain-voltage is equal to a source voltage of the common-gate transistor and the drain-voltage increases in response to switching the common-source transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first gate-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first gate-voltage and a second gate-voltage. The common-gate transistor is configured to switch to a second OFF state in response to receiving the second gate-voltage.

    BIAS CIRCUIT AND POWER AMPLIFIER CIRCUIT
    8.
    发明申请

    公开(公告)号:WO2020143934A1

    公开(公告)日:2020-07-16

    申请号:PCT/EP2019/073046

    申请日:2019-08-29

    摘要: A bias circuit (200) for a PA (100) is disclosed. It comprises a first transistor (M1) having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal (GND), a first current source (I1) connected to the first circuit node (x), and a first resistor (R1) connected between the first circuit node (x) and a second circuit node (y). It further comprises a second transistor (M2) configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD), and a third transistor (M3) configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD). The gate terminals of the second transistor (M2) and the third transistor (M3) are configured to be biased by a first voltage (V1). The bias circuit is configured to generate a bias voltage (Vbias) for the PA (100) at the second circuit node (y).

    増幅回路および受信回路
    10.
    发明申请

    公开(公告)号:WO2019142526A1

    公开(公告)日:2019-07-25

    申请号:PCT/JP2018/044520

    申请日:2018-12-04

    发明人: 吉川 直人

    IPC分类号: H03F3/191 H03F1/22 H03F3/45

    摘要: 本開示の増幅回路は、第1のノードに接続されたドレインを有する第1のトランジスタと、第2のノードに接続されたドレインを有する第2のトランジスタと、電流源と、第3のノードに接続されたゲートと、第1のノードに接続されたソースと、電源に接続されたドレインとを有する第3のトランジスタと、第3のノードに接続されたゲートと、第2のノードに接続されたソースと、電源に接続されたドレインとを有する第4のトランジスタと、複数の回路とを備える。複数の回路のそれぞれは、第4のノードに接続されたゲートと、第2のノードに接続されたソースとを有する第5のトランジスタと、第4のノードに接続されたゲートと、第1のノードに接続されたソースとを有する第6のトランジスタと、電源と第5および第6のトランジスタのドレインとの間に挿入された共振回路とを有する。