AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW
    1.
    发明申请
    AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW 审中-公开
    用于消除时钟的平均时间提取电路

    公开(公告)号:WO2007067634A3

    公开(公告)日:2008-07-03

    申请号:PCT/US2006046572

    申请日:2006-12-06

    CPC classification number: G06F1/105

    Abstract: A method involving: detecting a first signal characterized by a periodically occurring first event; detecting a second signal characterized by a periodically occurring second event; and based on both the detected first and second signals, generating a third signal characterized by a periodically occurring third event, wherein generating the third signal involves automatically adjusting the phase of the third signal so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.

    Abstract translation: 一种方法,涉及:检测以周期性发生的第一事件为特征的第一信号; 检测以周期性发生的第二事件为特征的第二信号; 并且基于检测到的第一和第二信号,产生以周期性发生的第三事件为特征的第三信号,其中产生第三信号涉及自动调整第三信号的相位,使得周期性发生的第三事件发生在预定位置之间 第一和第二信号的第一和第二事件。

    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION
    2.
    发明申请
    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION 审中-公开
    SKEW校正系统通过参考多项式消除相位偏差

    公开(公告)号:WO2007067631A3

    公开(公告)日:2008-04-03

    申请号:PCT/US2006046569

    申请日:2006-12-06

    Abstract: A system for generating a local clock signal, the system including: a skew correction circuit for receiving first and second periodic signals that have associated skews, wherein the skew correction circuit is configured to use the received first and second periodic signals to generate a third periodic signal that has a fixed skew between the skews of the first and second periodic signals; a phase detector with a first input that receives the third periodic signal from the skew correction circuit and a second input; a variable oscillator for generating an output signal having a frequency that is controlled by the phase detector; and a frequency divider for dividing the frequency of the oscillator's output signal, wherein the frequency-divided output signal is fed back to the second input of the phase detector, and wherein the local clock signal is derived from the oscillator's output signal.

    Abstract translation: 一种用于产生本地时钟信号的系统,所述系统包括:偏斜校正电路,用于接收具有相关偏斜的第一和第二周期信号,其中所述偏斜校正电路被配置为使用所接收的第一和第二周期信号来产生第三周期 信号在第一和第二周期信号的偏差之间具有固定的偏差; 相位检测器,具有从偏斜校正电路接收第三周期信号的第一输入端和第二输入端; 用于产生具有由所述相位检测器控制的频率的输出信号的可变振荡器; 以及分频器,用于分频振荡器的输出信号的频率,其中分频输出信号被反馈到相位检测器的第二输入端,并且其中本地时钟信号从振荡器的输出信号导出。

    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION
    3.
    发明申请
    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION 审中-公开
    SKEW校正系统通过参考多项式消除相位偏差

    公开(公告)号:WO2007067631A9

    公开(公告)日:2007-09-07

    申请号:PCT/US2006046569

    申请日:2006-12-06

    Abstract: A system for generating a local clock signal, the system including: a skew correction circuit for receiving first and second periodic signals that have associated skews, wherein the skew correction circuit is configured to use the received first and second periodic signals to generate a third periodic signal that has a fixed skew between the skews of the first and second periodic signals; a phase detector with a first input that receives the third periodic signal from the skew correction circuit and a second input; a variable oscillator for generating an output signal having a frequency that is controlled by the phase detector; and a frequency divider for dividing the frequency of the oscillator's output signal, wherein the frequency-divided output signal is fed back to the second input of the phase detector, and wherein the local clock signal is derived from the oscillator's output signal.

    Abstract translation: 一种用于产生本地时钟信号的系统,所述系统包括:偏斜校正电路,用于接收具有相关斜率的第一和第二周期信号,其中所述偏斜校正电路被配置为使用所接收的第一和第二周期信号来产生第三周期 信号在第一和第二周期信号的偏差之间具有固定的偏差; 相位检测器,具有从偏斜校正电路接收第三周期信号的第一输入端和第二输入端; 用于产生具有由相位检测器控制的频率的输出信号的可变振荡器; 以及分频器,用于分频振荡器的输出信号的频率,其中分频输出信号反馈到相位检测器的第二输入,并且其中本地时钟信号从振荡器的输出信号导出。

    AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW
    4.
    发明申请
    AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW 审中-公开
    用于消除时钟的平均时间提取电路

    公开(公告)号:WO2007067634A2

    公开(公告)日:2007-06-14

    申请号:PCT/US2006/046572

    申请日:2006-12-06

    CPC classification number: G06F1/105

    Abstract: A method involving: detecting a first signal characterized by a periodically occurring first event; detecting a second signal characterized by a periodically occurring second event; and based on both the detected first and second signals, generating a third signal characterized by a periodically occurring third event, wherein generating the third signal involves automatically adjusting the phase of the third signal so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.

    Abstract translation: 一种方法,涉及:检测以周期性发生的第一事件为特征的第一信号; 检测以周期性发生的第二事件为特征的第二信号; 并且基于检测到的第一和第二信号,产生以周期性发生的第三事件为特征的第三信号,其中产生第三信号涉及自动调整第三信号的相位,使得周期性发生的第三事件发生在预定位置之间 第一和第二信号的第一和第二事件。

    LOW COST, ACTIVE ANTENNA ARRAYS
    5.
    发明申请
    LOW COST, ACTIVE ANTENNA ARRAYS 审中-公开
    低成本,主动天线阵列

    公开(公告)号:WO2012003276A1

    公开(公告)日:2012-01-05

    申请号:PCT/US2011/042527

    申请日:2011-06-30

    CPC classification number: H04B7/0682 H01Q3/26

    Abstract: A transmitter system including: a bidirectional signaling (BDS) network having first and second networks for carrying first and second carrier signals, and having a set of n phase synchronous location pairs (a i , b i ),; and also including tunable transmitter circuits for driving an antenna array, each tunable transmitter circuit having an output line for carrying an output signal and first and second input lines electrically connected to the first and second networks of the BDS network at locations of a corresponding one of the set of phase synchronous location pairs, and including a multiplier having a first input electrically connected to the first input line of that tunable transmitter circuit; a phase setting circuit electrically connected to the multiplier for controlling the phase of the output signal of that tunable transmitter circuit; and an amplitude setting circuit for controlling the amplitude of the output signal of that tunable transmitter circuit.

    Abstract translation: 一种发射机系统,包括:双向信令(BDS)网络,具有用于承载第一和第二载波信号的第一和第二网络,并且具有一组n相同步位置对(ai,bi); 并且还包括用于驱动天线阵列的可调谐发射器电路,每个可调谐发射器电路具有用于承载输出信号的输出线和在BDS网络的相应一个的位置处电连接到BDS网络的第一和第二网络的第一和第二输入线 所述相位同步位置对的集合,并且包括具有电连接到所述可调谐发射器电路的第一输入线的第一输入的乘法器; 电连接到乘法器的相位设置电路,用于控制可调谐发射器电路的输出信号的相位; 以及用于控制该可调谐发射机电路的输出信号的振幅的幅度设定电路。

    AVERAGE TIME EXTRACTION BY MULTIPLICATION
    6.
    发明申请
    AVERAGE TIME EXTRACTION BY MULTIPLICATION 审中-公开
    通过多次平均时间提取

    公开(公告)号:WO2007070329A3

    公开(公告)日:2009-01-15

    申请号:PCT/US2006046686

    申请日:2006-12-06

    CPC classification number: H04L7/0008 G06F1/105

    Abstract: A method involving: in a signal distribution system including a first line and a second line both of which extend from the first end to the second end of the signal distribution system, introducing a first global clock signal into the first line so that the first global clock signal propagates from the first end to the second end of the line; introducing a second sinusoidal global clock signal into the second line so that the second global clock signal propagates from the second end to the first end of the line; and in each of a plurality of local clocking regions located along the signal distribution system, detecting the first and second global clock signals; multiplying the detected first and second clock signal for that local clocking region together to generate a combined signal, and deriving a local clock signal for that local clocking region from the combined signal.

    Abstract translation: 一种方法,包括:在包括从信号分配系统的第一端延伸到第二端的第一线和第二线的信号分配系统中,将第一全局时钟信号引入到第一线中,使得第一全局 时钟信号从线的第一端传播到第二端; 将第二正弦全局时钟信号引入第二行,使得第二全局时钟信号从第二端传播到线的第一端; 以及沿着信号分配系统定位的多个本地时钟区域中的每一个,检测第一和第二全局时钟信号; 将检测到的第一和第二时钟信号与该本地时钟区域相乘,以产生组合信号,并从该组合信号中导出该本地时钟区域的本地时钟信号。

    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION
    7.
    发明申请
    SKEW CORRECTION SYSTEM ELIMINATING PHASE AMBIGUITY BY USING REFERENCE MULTIPLICATION 审中-公开
    偏移校正系统利用参考倍增消除相位失真

    公开(公告)号:WO2007067631A2

    公开(公告)日:2007-06-14

    申请号:PCT/US2006/046569

    申请日:2006-12-06

    Abstract: A system for generating a local clock signal, the system including: a skew correction circuit for receiving first and second periodic signals that have associated skews, wherein the skew correction circuit is configured to use the received first and second periodic signals to generate a third periodic signal that has a fixed skew between the skews of the first and second periodic signals; a phase detector with a first input that receives the third periodic signal from the skew correction circuit and a second input; a variable oscillator for generating an output signal having a frequency that is controlled by the phase detector; and a frequency divider for dividing the frequency of the oscillator's output signal, wherein the frequency-divided output signal is fed back to the second input of the phase detector, and wherein the local clock signal is derived from the oscillator's output signal.

    Abstract translation: 一种用于产生本地时钟信号的系统,所述系统包括:偏斜校正电路,用于接收具有相关联偏斜的第一和第二周期性信号,其中所述偏斜校正电路被配置为使用所接收的第一和第二周期性信号 第二周期性信号以产生第三周期性信号,该第三周期性信号在第一和第二周期性信号的偏斜之间具有固定偏斜; 具有第一输入端和第二输入端的相位检测器,所述第一输入端接收来自所述偏斜校正电路的第三周期性信号; 可变振荡器,用于生成具有由相位检测器控制的频率的输出信号; 以及用于分频振荡器输出信号的频率的分频器,其中分频输出信号被反馈到相位检测器的第二输入端,并且其中本地时钟信号是从振荡器的输出信号中导出的。 >

    AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW
    8.
    发明申请
    AVERAGE TIME EXTRACTION CIRCUIT FOR ELIMINATING CLOCK SKEW 审中-公开
    用于消除时钟的平均时间提取电路

    公开(公告)号:WO2007067608A2

    公开(公告)日:2007-06-14

    申请号:PCT/US2006/046531

    申请日:2006-12-06

    CPC classification number: G06F1/105

    Abstract: A method and apparatus for receiving a first signal characterized by a periodically occurring first event; receiving a second signal characterized by a periodically occurring second event; delaying the first signal by a controllable amount of delay to generate a third signal characterized by a periodically occurring third event; and based on relative timing of the first and second signals, controlling the amount of delay so that the periodically occurring third event occurs at a predetermined location between the first and second events of the first and second signals.

    Abstract translation: 一种用于接收以周期性发生的第一事件为特征的第一信号的方法和装置; 接收以周期性发生的第二事件为特征的第二信号; 将第一信号延迟可控量的延迟以产生以周期性发生的第三事件为特征的第三信号; 并且基于第一和第二信号的相对定时,控制延迟量,使得周期性发生的第三事件发生在第一和第二信号的第一和第二事件之间的预定位置处。

    AC TECHNIQUE FOR ELIMINATING PHASE AMBIGUITY IN CLOCKING SIGNALS
    10.
    发明申请
    AC TECHNIQUE FOR ELIMINATING PHASE AMBIGUITY IN CLOCKING SIGNALS 审中-公开
    用于消除时钟信号中相位优先的交流技术

    公开(公告)号:WO2007067609A3

    公开(公告)日:2008-08-07

    申请号:PCT/US2006046536

    申请日:2006-12-06

    Abstract: A method involving: distributing two clock signals over a clock signal distribution system; in each of a plurality local clocking regions located along the signal distribution system, detecting the two clock signals and generating therefrom a local clock signal for that local clocking region, wherein the generated local clock signals for at least some of the plurality of local clocking regions are in a first group all of which are aligned in phase with each other and the generated local clock signals for the remainder of the plurality of local clocking regions are in a second group all of which are aligned in phase with each other, and wherein the phase of the first group is out of phase with the phase of the second group by a predetermined amount; and bringing all of the clock signals for the plurality of local clocking regions into phase alignment so that the phase of the first group is in phase with the phase of the second group.

    Abstract translation: 一种方法,包括:通过时钟信号分配系统分配两个时钟信号; 在沿着所述信号分配系统定位的多个本地时钟区域中的每一个中,检测所述两个时钟信号并从其产生用于所述本地时钟区域的本地时钟信号,其中所产生的本地时钟信号用于所述多个本地时钟区域中的至少一些 处于第一组中,所有这些组彼此相位对准,并且多个本地时钟区域的其余部分的所产生的本地时钟信号处于第二组中,所有这些本体时钟信号彼此同相对齐,并且其中, 第一组的相位与第二组的相位异相预定量; 并将多个本地时钟区域的所有时钟信号引入相位对准,使得第一组的相位与第二组的相位同相。

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