公开(公告)号：WO2005119412A1

公开(公告)日：2005-12-15

申请号：PCT/EP2005/051797

申请日：2005-04-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  HELLER, JR., Thomas ,  IGNATOWSKI, Michael ,  MEYERSON, Bernard, Steele ,  RYMARCZYK, James, Walter

Inventor： HELLER, JR., Thomas ,  IGNATOWSKI, Michael ,  MEYERSON, Bernard, Steele ,  RYMARCZYK, James, Walter

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30101 ,  G06F9/3885 ,  Y02D10/171 ,  Y02D50/20

Abstract: A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are used to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified.

Abstract translation: 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别用于执行该过程的硬件元素。 通过改变所识别的硬件元件的当前功率状态来动态地改变微处理器芯片中的功率。

公开(公告)号：WO2005001693A2

公开(公告)日：2005-01-06

申请号：PCT/EP2004/050878

申请日：2004-05-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  HELLER, Thomas ,  BAUM, Richard ,  IGNATOWSKI, Michael ,  RYMARCZYK, James

Inventor： HELLER, Thomas ,  BAUM, Richard ,  IGNATOWSKI, Michael ,  RYMARCZYK, James

IPC: G06F12/00

CPC classification number: G06F12/0831 ,  G06F12/0824

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a hypervisor.

Abstract translation: 多处理器计算机系统具有多个处理节点，其使用处理器状态信息来确定系统中哪些相干高速缓存需要检查由单个发起处理器的存储请求产生的一致性事务。 计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大型系统中的单个工作负载的总处理器的子集，并且可以在主管软件或固件扩展和收缩时优化高速缓存一致性 用于运行任何单个工作负载的处理器数量。 节点的多个实例可以与第二级控制器连接，以创建大型多处理器系统。 节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收的任何给定事务。 第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。 逻辑分区映射到允许的物理处理器。 选择包含系统中总处理器和高速缓存的子集的高速缓存相干区域用于物理接近。 可以使用管理程序为每个分区定义不同的高速缓存一致性区域。

公开(公告)号：WO2005001693A3

公开(公告)日：2005-03-31

申请号：PCT/EP2004050878

申请日：2004-05-25

Applicant: IBM ,  IBM UK ,  HELLER THOMAS ,  BAUM RICHARD ,  IGNATOWSKI MICHAEL ,  RYMARCZYK JAMES

Inventor： HELLER THOMAS ,  BAUM RICHARD ,  IGNATOWSKI MICHAEL ,  RYMARCZYK JAMES

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0824

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller. The second level controller uses the mode bits to determine which nodes must receive any given transaction that is received by the second level controller. Logical partitions are mapped to allowable physical processors. Cache coherence regions which encompass subsets of the total number of processors and caches in the system are chosen for their physical proximity. A distinct cache coherency region can be defined for each partition using a hypervisor.

Abstract translation: 多处理器计算机系统具有多个处理节点，这些处理节点使用处理器状态信息来确定系统中的哪些相干高速缓存需要检查由单个始发处理器的存储请求产生的一致性事务。 计算机的节点具有动态一致性边界，使得硬件在任何特定时间点仅使用大系统中的全部处理器的子集用于单个工作负载，并且可以随着监控软件或固件扩展和合同而优化高速缓存一致性 正在用于运行任何单个工作负载的处理器数量。 一个节点的多个实例可以连接到一个二级控制器来创建一个大的多处理器系统。 节点控制器使用模式位来确定哪些处理器必须接收节点控制器接收到的任何给定事务。 第二级控制器使用模式位来确定哪些节点必须接收由第二级控制器接收的任何给定事务。 逻辑分区映射到允许的物理处理器。 包含系统中处理器和高速缓存总数的子集的高速缓存一致性区域被选择用于它们的物理接近度。 可以使用管理程序为每个分区定义不同的高速缓存一致性区域。