公开(公告)号：WO2011145025A1

公开(公告)日：2011-11-24

申请号：PCT/IB2011/052068

申请日：2011-05-11

申请人： NXP B.V ,  REIMANN, Klaus ,  STEENEKEN, Peter G ,  VAN LEUKEN-PETERS, Linda ,  ROEST, Aarnoud L ,  WUNNICKE, Olaf ,  GOOSSENS, Martijn

发明人： REIMANN, Klaus ,  STEENEKEN, Peter G ,  VAN LEUKEN-PETERS, Linda ,  ROEST, Aarnoud L ,  WUNNICKE, Olaf ,  GOOSSENS, Martijn

IPC分类号： H04R23/00

CPC分类号： H04R23/008

摘要： A microphone comprises a planar substrate arrangement, an optical source provided over the substrate arrangement for emitting a light beam in a direction parallel to the substrate arrangement and a layer structure defining at least one optical cavity through which the light beam is directed, the cavity exposed to the sound pressure to be sensed. The light beam is directed to a target after passing through the cavity. Optical analysis is used for determining an optical property which is dependent on the pressure in the cavity.

摘要翻译： 麦克风包括平面衬底布置，设置在衬底布置上用于沿平行于衬底布置的方向发射光束的光源以及限定光束被引导的至少一个光腔的层结构，腔暴露 到要感测的声压。 光束在通过空腔后被引导到目标。 光学分析用于确定取决于空腔中的压力的​​光学性质。

公开(公告)号：WO2010122454A1

公开(公告)日：2010-10-28

申请号：PCT/IB2010/051612

申请日：2010-04-14

申请人： NXP B.V. ,  ROEST, Aarnoud Laurens ,  VAN LEUKEN-PETERS, Linda

发明人： ROEST, Aarnoud Laurens ,  VAN LEUKEN-PETERS, Linda

IPC分类号： H01L21/02 ,  H01L27/01 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L28/55 ,  H01L27/016 ,  H01L27/0251 ,  H01L27/0688 ,  H01L28/20 ,  H01L28/65

摘要： The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate (102) at least one integrated MIM capacitor (114) having a top capacitor electrode (118) and a bottom capacitor electrode (112) at a smaller distance from the substrate than the top capacitor electrode; fabricating an electrically insulating first cover layer (120) on the top capacitor electrode, which first cover layer partly or fully covers the top capacitor electrode and is made of a lead- containing dielectric material; thinning the first cover layer; fabricating an electrically insulating second cover layer (124) on the first cover layer, which second cover layer partly or fully covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and fabricating an electrically conductive resistor layer (126) on the second cover layer, which resistor layer has a defined ohmic resistance.

摘要翻译： 本发明涉及一种电子部件的制造方法，其特征在于，在基板（102）上，在具有顶部电容电极（118）和底部电容电极（112）的至少一个集成MIM电容器（114）的基板 与顶部电容器电极距离衬底; 在顶部电容器电极上制造电绝缘的第一覆盖层（120），所述第一覆盖层部分或完全覆盖顶部电容器电极并且由含铅介电材料制成; 使第一覆盖层变薄; 在所述第一覆盖层上制造电绝缘的第二覆盖层（124），所述第二覆盖层部分或完全覆盖所述第一覆盖层并且具有比所述第一覆盖层的介电常数小的介电常数; 以及在所述第二覆盖层上制造导电电阻层（126），所述电阻层具有限定的欧姆电阻。

公开(公告)号：WO2010076733A1

公开(公告)日：2010-07-08

申请号：PCT/IB2009/055887

申请日：2009-12-21

申请人： NXP B.V. ,  ROEST, Aarnoud, Laurens ,  VAN LEUKEN-PETERS, Linda ,  WOLTERS, Robertus, Adrianus, Maria

发明人： ROEST, Aarnoud, Laurens ,  VAN LEUKEN-PETERS, Linda ,  WOLTERS, Robertus, Adrianus, Maria

IPC分类号： H01L23/58

CPC分类号： H01L23/576 ,  G06F21/73 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a semiconductor device comprising a physical structure (50) for use in a physical unclonable function, wherein the physical structure (50) comprises a lead-zirconium titanate layer (25), and a silicon-comprising dielectric layer (27) deposited on the lead-zirconium-titanate layer (25), wherein the silicon-comprising dielectric layer (27) has a rough surface (SR), the physical structure (50) further comprising a conductive layer (30) provided on the rough surface (SR) of the silicon-comprising dielectric layer (27). The invention further relates to a method of manufacturing such semiconductor device. The invention also relates to a card, such as a smartcard, and to a RFID tag comprising such semiconductor device. The inventors have found that depositing of a silicon- comprising dielectric layer (27) on a lead-zirconium titanate layer (25) using vapor deposition results in a silicon-comprising dielectric layer (27) having a rough surface (SR). This rough surface (SR) can be used in a PUF to make a resistor (R) with a variable random value by depositing a conductive layer (30) on the rough surface (SR). Alternatively, the combination of both layers (25, 27) can be used in a PUF as composite dielectric to make a capacitor (C) with a variable random capacitance value.

摘要翻译： 本发明涉及一种半导体器件，其包括用于物理不可克隆功能的物理结构（50），其中所述物理结构（50）包括钛酸铅锆层（25）和含硅介电层（27） 沉积在铅钛酸锆层（25）上，其中含硅介电层（27）具有粗糙表面（SR），物理结构（50）还包括设置在粗糙表面上的导电层（30） （27）的硅（SR）。 本发明还涉及制造这种半导体器件的方法。 本发明还涉及诸如智能卡的卡，以及包括这种半导体器件的RFID标签。 本发明人已经发现，使用气相沉积在含钛的钛酸铅层（25）上沉积含硅的介电层（27）导致具有粗糙表面（SR）的含硅介电层（27）。 通过在粗糙表面（SR）上沉积导电层（30），该粗糙表面（SR）可用于PUF中以制造具有可变随机值的电阻器（R）。 或者，两层（25,27）的组合可以用作PUF作为复合电介质，以制造具有可变随机电容值的电容器（C）。

公开(公告)号：WO2010049859A1

公开(公告)日：2010-05-06

申请号：PCT/IB2009/054678

申请日：2009-10-22

申请人： NXP B.V. ,  ROEST, Aarnoud, Laurens ,  KLEE, Mareike ,  MAUCZOK, Rudiger, Gunter ,  VAN LEUKEN-PETERS, Linda ,  WOLTERS, Robertus, Adrianus, Maria

发明人： ROEST, Aarnoud, Laurens ,  KLEE, Mareike ,  MAUCZOK, Rudiger, Gunter ,  VAN LEUKEN-PETERS, Linda ,  WOLTERS, Robertus, Adrianus, Maria

IPC分类号： H01L21/02 ,  H01L23/522 ,  H01L27/02 ,  H01L27/06

CPC分类号： H01L28/55 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0688 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

摘要翻译： 电子部件技术领域本发明涉及一种电子部件，其在基板上包括至少一个集成MIM电容器，（114）部分地或完全覆盖顶部电容器电极（118）并被制成的电绝缘的第一覆盖层（120） 的含铅介电材料，以及在第一覆盖层上的顶部阻挡层（122）。 顶部阻挡层用于避免在第一覆盖层暴露于还原物质时第一覆盖层所包含的引线原子的还原。 在顶部阻挡层上的电绝缘的第二覆盖层（124）的介电常数比第一覆盖层的介电常数小，从而形成覆盖层结构的低寄生电容。 所描述的具有中间顶部阻挡层的覆盖层结构允许在顶部制造高精度电阻层（126.1）。