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    ITERATIVE DECODER SYSTEMS AND METHODS
    3.
    发明申请
    ITERATIVE DECODER SYSTEMS AND METHODS 审中-公开
    迭代解码器系统和方法

    公开(公告)号：WO2009075831A2

    公开(公告)日：2009-06-18

    申请号：PCT/US2008013531

    申请日：2008-12-08

    Applicant: MARVELL INT LTD ,  CHAICHANAVONG PANU ,  VARNICA NEDELJKO ,  NANGARE NITIN ,  BURD GREGORY ,  WU ZINING

    Inventor： CHAICHANAVONG PANU ,  VARNICA NEDELJKO ,  NANGARE NITIN ,  BURD GREGORY ,  WU ZINING

    IPC: G11B20/18 ,  H03M13/11 ,  H03M13/41

    CPC classification number: H03M13/41 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2020/10759 ,  G11B2020/1457 ,  H03M13/09 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1114 ,  H03M13/13 ,  H03M13/29 ,  H03M13/2948 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561

    Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

    Abstract translation: 提供系统和方法用于改进迭代解码器系统的设计和性能。 在一些实施例中，迭代解码器可以通过FIR RAM与FIR采样解耦，从而导致较不复杂的设计和较短的处理时间。 在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时可以使用中间存储器。 在一些实施例中，可以在每个LDPC迭代期间从从LDPC接收的信息连续地序列化SOVA需要的信息。 在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行1 /（1 + D）预编码器。 一个1 /（1 + D）预编码器可以拉出HR RLL编码器的外部，并与迭代解码器一起使用。 这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器强加给编码信息的RLL约束。

    STORAGE AGGREGATOR CONTROLLER WITH METADATA COMPUTATION CONTROL
    4.
    发明申请
    STORAGE AGGREGATOR CONTROLLER WITH METADATA COMPUTATION CONTROL 审中-公开

    公开(公告)号：WO2020028597A1

    公开(公告)日：2020-02-06

    申请号：PCT/US2019/044558

    申请日：2019-07-31

    Applicant: MARVELL WORLD TRADE LTD. ,  VARNICA, Nedeljko ,  FUREY, Scott ,  SHRIVASTAVA, Manish ,  MIZRAHI, Noam

    Inventor： VARNICA, Nedeljko ,  FUREY, Scott ,  SHRIVASTAVA, Manish ,  MIZRAHI, Noam

    IPC: G06F16/41

    Abstract: This disclosure describes a storage aggregator controller with metadata computation control, The storage aggregator controller communicates, via a host interface, over a computer network with one or more remote hosts, and also communicates, via a storage device interface, with a plurality of local storage devices, which are separate from the remote host(s) and which have respective non-volatile memories. The storage aggregator controller manages the local storage devices for storage or retrieval of media objects. The storage aggregator controller also governs a selective computation, at aggregator control circuitry or at a storage device controller of one or more of the storage devices, of metadata that defines content characteristics of the media objects that are retrieved from the plurality of storage devices or that are received from the one or more hosts over the computer network for storage in the plurality of storage devices.

    ITERATIVE DECODER SYSTEMS AND METHODS
    6.
    发明申请
    ITERATIVE DECODER SYSTEMS AND METHODS 审中-公开

    公开(公告)号：WO2009075831A3

    公开(公告)日：2009-06-18

    申请号：PCT/US2008/013531

    申请日：2008-12-08

    Applicant: MARVELL INTERNATIONAL LTD. ,  CHAICHANAVONG, Panu ,  VARNICA, Nedeljko ,  NANGARE, Nitin ,  BURD, Gregory ,  WU, Zining

    Inventor： CHAICHANAVONG, Panu ,  VARNICA, Nedeljko ,  NANGARE, Nitin ,  BURD, Gregory ,  WU, Zining

    IPC: G11B20/18 ,  H03M13/41 ,  H03M13/11

    Abstract: Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D 2 ) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

    BIT FLIPPING DECODING WITH RELIABILITY INPUTS FOR LDPC CODES
    7.
    发明申请
    BIT FLIPPING DECODING WITH RELIABILITY INPUTS FOR LDPC CODES 审中-公开
    用于LDPC码的可靠性输入的位移解码

    公开(公告)号：WO2014126750A1

    公开(公告)日：2014-08-21

    申请号：PCT/US2014/014697

    申请日：2014-02-04

    Applicant: MARVELL WORLD TRADE LTD. ,  VARNICA, Nedeljko ,  NGUYEN, Dung, Viet ,  CHILAPPAGARI, Shashi, Kiran

    Inventor： VARNICA, Nedeljko ,  NGUYEN, Dung, Viet ,  CHILAPPAGARI, Shashi, Kiran

    IPC: H03M13/11 ,  H03M13/45

    CPC classification number: H03M13/1108 ,  H03M13/1137 ,  H03M13/1171

    Abstract: Systems and methods are provided for bit flipping decoding with reliability inputs for LDPC codes. An LDPC decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an updated check node value based on the updated variable node value. An update rule may be based on whether checks of the variable node value are satisfied or unsatisfied, whether the variable node value has been previously updated, flipped, or toggled, based on the value of the reliability data, or a suitable combination thereof.

    Abstract translation: 提供了用于LDPC码的可靠性输入的位翻转解码的系统和方法。 LDPC解码器接收变量节点的可变节点值和可靠性数据，并且检查与变量节点相关联的校验节点的节点值。 电路根据接收的可靠性数据和接收到的校验节点值产生更新的变量节点值。 对于至少一个校验节点，电路还基于更新的变量节点值生成更新的校验节点值。 更新规则可以基于是否满足或不满足变量节点值的检查，基于可靠性数据的值或其适当的组合，变量节点值是否已经被先前更新，翻转或切换。

    LDPC MULTI-DECODER ARCHITECTURES
    8.
    发明申请
    LDPC MULTI-DECODER ARCHITECTURES 审中-公开
    LDPC多解码器架构

    公开(公告)号：WO2012097046A1

    公开(公告)日：2012-07-19

    申请号：PCT/US2012/020910

    申请日：2012-01-11

    Applicant: MARVELL WORLD TRADE LTD. ,  VARNICA, Nedeljko ,  BURD, Gregory

    Inventor： VARNICA, Nedeljko ,  BURD, Gregory

    IPC: H03M13/37 ,  H03M13/11

    CPC classification number: H03M13/1108 ,  H03M13/1117 ,  H03M13/1128 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2909 ,  H03M13/3707

    Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix. The super matrix corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder. The super-parity- check matrix includes n parity check matrices. The parity check matrices include x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows corresponding to nx check node processing elements and ny columns corresponding to ny bit node processing elements. The numbers n, x, and y are selected so that ny codeword bits corresponding to the super-parity-check matrix can be processed in single time unit by the high throughput decoder and y codeword bits corresponding to the super-parity- check matrix can be processed in a single time unit by the low throughput decoder.

    Abstract translation: 描述了与LDPC解码器架构相关联的系统，方法和其他实施例。 根据一个实施例，一种装置包括超奇偶校验矩阵。 超矩阵对应于低密度奇偶校验（LDPC）码矩阵的至少一部分。 超奇偶校验矩阵耦合到高吞吐量LDPC解码器和低吞吐量LDPC解码器。 超奇偶校验矩阵包括n个奇偶校验矩阵。 奇偶校验矩阵包括对应于x校验节点处理元素的x行和对应于y位节点处理元素的y列。 因此，超奇偶校验矩阵包括对应于n×校验节点处理元素的nx行和对应于ny位节点处理元素的ny列。 选择数字n，x和y，使得与超奇偶校验矩阵相对应的ny码字比特可以由高吞吐量解码器以及对应于超奇偶校验矩阵的y码字比特以单个时间单位处理 由低吞吐量解码器以单个时间单位进行处理。

    IMPROVED PERFORMANCE OF CODING SCHEMES
    9.
    发明申请
    IMPROVED PERFORMANCE OF CODING SCHEMES 审中-公开
    改进编码方案的性能

    公开(公告)号：WO2005077108A3

    公开(公告)日：2008-10-02

    申请号：PCT/US2005004500

    申请日：2005-02-09

    Applicant: HARVARD COLLEGE ,  UNIV HAWAII ,  VARNICA NEDELJKO ,  KAVCIC ALEKSANDAR ,  FOSSORIER MARC

    Inventor： VARNICA NEDELJKO ,  KAVCIC ALEKSANDAR ,  FOSSORIER MARC

    IPC: G06F11/00 ,  H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1111 ,  H03M13/3723 ,  H03M13/3738

    Abstract: Improved decoding techniques for linear block codes, such as low-density parity-check (LDPC) codes (500). In one example, modifications to a conventional belief-propagation (BP) decoding algorithm (50A) for LDPC codes significantly improve the performance of the decoding algorithm so as to more closely approximate that of the theoretically optimal maximum-likelihood (ML) decoding scheme. BP decoder (50A) performance generally is improved for lower code block lengths, and significant error floor reduction or elimination may be achieved for higher code block lengths (82). In one aspect, significantly improved performance of a modified BP algorithm is achieved while at the same time essentially maintaining the benefits of relative computational simplicity and execution speed of a conventional BP algorithm as compared to an ML decoding scheme (51).

    Abstract translation: 用于线性块码的改进的解码技术，例如低密度奇偶校验（LDPC）码（500）。 在一个示例中，对用于LDPC码的常规置信度传播（BP）解码算法（50A）的修改显着地提高了解码算法的性能，从而更接近于理论上最佳最大似然（ML）解码方案的性能。 BP解码器（50A）的性能通常在较低代码块长度方面得到改进，并且对于较高的代码块长度（82）可以实现显着的误差降低或消除。 在一方面，与ML解码方案（51）相比，实现了改进的BP算法的显着改进的性能，同时基本上保持了常规BP算法的相对计算简单性和执行速度的优点。

    METHODS AND APPARATUS FOR IMPROVING PERFORMANCE OF INFORMATION CODING SCHEMES
    10.
    发明申请
    METHODS AND APPARATUS FOR IMPROVING PERFORMANCE OF INFORMATION CODING SCHEMES 审中-公开
    改进信息编码方案性能的方法和装置

    公开(公告)号：WO2005077108A2

    公开(公告)日：2005-08-25

    申请号：PCT/US2005/004500

    申请日：2005-02-09

    Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE ,  UNIVERSITY OF HAWAII ,  VARNICA, Nedeljko ,  KAVCIC, Aleksandar ,  FOSSORIER, Marc

    Inventor： VARNICA, Nedeljko ,  KAVCIC, Aleksandar ,  FOSSORIER, Marc

    IPC: G06F11/00 ,  H03M13/00 ,  H03M13/11

    CPC classification number: H03M13/1111 ,  H03M13/3723 ,  H03M13/3738

    Abstract: Various modifications to conventional information coding schemes that result in an improvement in one or more performance measures for a given coding scheme. Some examples are directed to improved decoding techniques for linear block codes, such as low-density parity-check (LDPC) codes. In one example, modifications to a conventional belief-propagation (BP) decoding algorithm for LDPC codes significantly improve the performance of the decoding algorithm so as to more closely approximate that of the theoretically optimal maximum-likelihood (ML) decoding scheme. BP decoder performance generally is improved for lower code block lengths, and significant error floor reduction or elimination may be achieved for higher code block lengths. In one aspect, significantly improved performance of a modified BP algorithm is achieved while at the same time essentially maintaining the benefits of relative computational simplicity and execution speed of a conventional BP algorithm as compared to an ML decoding scheme. In another aspect, modifications for improving the performance of conventional BP decoders are universally applicable to "off the shelf' LDPC encoder/decoder pairs. Furthermore, the concepts underlying the various methods and apparatus disclosed herein may be more generally applied to various decoding schemes involving iterative decoding algorithms and message-passing on graphs, as well as coding schemes other than LDPC codes to similarly improve their performance. Exemplary applications for improved coding schemes include wireless (mobile) networks, satellite communication systems, optical communication systems, and data recording and storage systems (e.g., CDs, DVDs, hard drives, etc.).

    Abstract translation: 对传统信息编码方案的各种修改导致针对给定编码方案的一个或多个性能测量的改进。 一些示例涉及用于线性块码的改进的解码技术，例如低密度奇偶校验（LDPC）码。 在一个示例中，对用于LDPC码的常规置信传播（BP）解码算法的修改显着地提高了解码算法的性能，从而更接近于理论上最佳最大似然（ML）解码方案的性能。 对于较低的代码块长度，BP解码器性能通常得到改善，并且对于较高的代码块长度，可以实现显着的误差底板减少或消除。 在一个方面，与ML解码方案相比，实现了改进的BP算法的显着改进的性能，同时基本上保持了常规BP算法的相对计算简单性和执行速度的优点。 在另一方面，用于改进常规BP解码器的性能的修改通常适用于“现成的”LDPC编码器/解码器对。此外，本文公开的各种方法和装置的基础概念可以更一般地应用于涉及 迭代解码算法和图形上的消息传递，以及除LDPC码之外的编码方案，以类似地提高其性能。用于改进的编码方案的示例性应用包括无线（移动）网络，卫星通信系统，光通信系统和数据记录， 存储系统（例如，CD，DVD，硬盘驱动器等）。

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