公开(公告)号：WO2005020207A1

公开(公告)日：2005-03-03

申请号：PCT/US2004/026784

申请日：2004-08-18

Applicant: BRILLIAN CORPORATION ,  WATERMAN, John, Karl

Inventor： WATERMAN, John, Karl

IPC: G09G3/36

CPC classification number: G09G3/2011 ,  G09G3/36 ,  G09G5/12 ,  G09G5/18 ,  G09G2300/023 ,  G09G2300/026 ,  G09G2310/0297 ,  G09G2320/0233

Abstract: Methods and apparatus are provided for driving a liquid crystal microdisplay. The apparatus comprises more than one display driver integrated circuit where a liquid crystal microdisplay receives video information from at least two separate and distinct display driver integrated circuits. One of the display driver integrated circuits is designated as producing a master clock. The internal clocks of the other display driver integrated circuits are compared to the master clock and adjusted to reduce the phase difference to a delay that does not produce visible artifacts on the microdisplay. The frame polarity is compared to be the same from each integrated circuit driving the microdisplay before outputting video information. A frame synchronization signal is also generated from each display driver integrated circuit to ensure that they are all ready to provide information to the microdisplay.

Abstract translation: 提供用于驱动液晶微显示器的方法和装置。 该装置包括多于一个显示驱动器集成电路，其中液晶微显示器从至少两个独立和不同的显示驱动器集成电路接收视频信息。 显示驱动器集成电路之一被指定为产生主时钟。 将其他显示驱动器集成电路的内部时钟与主时钟进行比较，并将其调整为将相位差减小到在微显示器上不产生可见伪影的延迟。 将帧极性与在输出视频信息之前驱动微型显示器的每个集成电路进行比较。 还从每个显示驱动器集成电路产生帧同步信号，以确保它们都准备好向微显示器提供信息。

公开(公告)号：WO2003101083A3

公开(公告)日：2003-12-04

申请号：PCT/US2002/031647

申请日：2002-10-02

Applicant: THREE-FIVE SYSTEMS, INC. ,  WATERMAN, John, Karl

Inventor： WATERMAN, John, Karl

IPC: G09G3/20

Abstract: A memory management circuit manages frame data for a display system such as used in a projection television system or cellular phone. The frame data includes frames corresponding to a series of images for viewing by a user. The memory manager includes an input buffer to receive the frame data, a memory interface coupled to receive the frame data from the input buffer, and an output buffer coupled to receive the frame data from the memory interface and output the frame data to a display such as a liquid crystal (LCD) micro-display. The memory interface sends and receives the frame data as packets, with each packet having a size less than a full frame, to and from an external memory able to store at least one full frame of data.

公开(公告)号：WO2003101083A2

公开(公告)日：2003-12-04

申请号：PCT/US2002/031647

申请日：2002-10-02

Applicant: THREE-FIVE SYSTEMS, INC. ,  WATERMAN, John, Karl

Inventor： WATERMAN, John, Karl

IPC: H04N

CPC classification number: G09G5/005 ,  G09G5/006 ,  G09G5/393 ,  G09G5/395 ,  G09G5/399 ,  G09G2360/128 ,  H04N5/907 ,  H04N7/0132 ,  H04N2005/745

Abstract: A memory management circuit manages frame data for a display system such as used in a projection television system or cellular phone. The frame data includes frames corresponding to a series of images for viewing by a user. The memory manager includes an input buffer to receive the frame data, a memory interface coupled to receive the frame data from the input buffer, and an output buffer coupled to receive the frame data from the memory interface and output the frame data to a display such as a liquid crystal (LCD) micro-display. The memory interface sends and receives the frame data as packets, with each packet having a size less than a full frame, to and from an external memory able to store at least one full frame of data.

Abstract translation: 存储器管理电路管理诸如在投影电视系统或蜂窝电话中使用的显示系统的帧数据。 帧数据包括与一系列用于用户观看的图像相对应的帧。 存储器管理器包括用于接收帧数据的输入缓冲器，耦合以从输入缓冲器接收帧数据的存储器接口，以及耦合到从存储器接口接收帧数据的输出缓冲器，并将帧数据输出到诸如 作为液晶（LCD）微显示器。 存储器接口发送和接收帧数据作为分组，其中每个分组具有小于全帧的大小，能够存储能够存储至少一个全帧数据的外部存储器。