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公开(公告)号:WO2005123228A2
公开(公告)日:2005-12-29
申请号:PCT/US2005019652
申请日:2005-06-02
Applicant: FAIRCHILD IMAGING , LIU XINQIAO , WEN DAVID D , VU AHN N , ONISHI STEVEN KIYOSHI , ARDUINI CHARLES J
Inventor: LIU XINQIAO , WEN DAVID D , VU AHN N , ONISHI STEVEN KIYOSHI , ARDUINI CHARLES J
CPC classification number: H04N5/3577 , H04N5/372 , H04N5/378
Abstract: An imaging array having a CCD imaging array[10] that includes a plurality of pixels[15] that accumulate charge when exposed to light and a readout amplifier[30] is disclosed. The readout amplifier includes an operational amplifier[32] having an input and an output port and a feedback capacitor[33] connecting the input and output ports and a variable impedance path[35] between the input and output ports, the path having an impedance controlled by a reset signal. A reset signal generator[ 173] generates the reset signal in three sequential phases in which the path between the input and output ports has three impedance values to provide a starting voltage at the amplifier input prior to the measurement of charge from each pixel that has reduced noise.
Abstract translation: 公开了一种具有CCD成像阵列[10]的成像阵列,其包括在暴露于光时积累电荷的多个像素[15]和读出放大器[30]。 读出放大器包括具有输入和输出端口的运算放大器[32]和连接输入和输出端口的反馈电容器[33]和输入和输出端口之间的可变阻抗路径[35],该路径具有阻抗 由复位信号控制。 复位信号发生器[173]以三个连续的相位产生复位信号,其中输入和输出端口之间的路径具有三个阻抗值,以在从已经减少的每个像素的电荷测量之前在放大器输入端提供启动电压 噪声。
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公开(公告)号:WO2005123228A3
公开(公告)日:2005-12-29
申请号:PCT/US2005/019652
申请日:2005-06-02
Applicant: FAIRCHILD IMAGING , LIU, Xinqiao , WEN, David, D. , VU, Ahn, N. , ONISHI, Steven, Kiyoshi , ARDUINI, Charles, J.
Inventor: LIU, Xinqiao , WEN, David, D. , VU, Ahn, N. , ONISHI, Steven, Kiyoshi , ARDUINI, Charles, J.
IPC: B01D59/44
Abstract: An imaging array having a CCD imaging array[10] that includes a plurality of pixels[15] that accumulate charge when exposed to light and a readout amplifier[30] is disclosed. The readout amplifier includes an operational amplifier[32] having an input and an output port and a feedback capacitor[33] connecting the input and output ports and a variable impedance path[35] between the input and output ports, the path having an impedance controlled by a reset signal. A reset signal generator[ 173] generates the reset signal in three sequential phases in which the path between the input and output ports has three impedance values to provide a starting voltage at the amplifier input prior to the measurement of charge from each pixel that has reduced noise.
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