公开(公告)号：WO2006014501A3

公开(公告)日：2006-07-27

申请号：PCT/US2005024009

申请日：2005-07-06

Applicant: AMALFI SEMICONDUCTOR INC ,  BURNS LAWRENCE M ,  WOO CHONG L

Inventor： BURNS LAWRENCE M ,  WOO CHONG L

IPC: H03F3/68

CPC classification number: H03F3/604 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/198 ,  H03F2200/435 ,  H03F2200/541 ,  H03F2203/45058

Abstract: A power amplifier uses parallel amplification (102, 104 and 106) and at least two levels of power combining (108, 110, 112 and 118) to manage peak-to-peak voltage swings, so as to reduce the likelihood of voltage breakdown at individual transistors. Each level of power combining provides an upward impedance transformation. For example, both levels of power combining may double the impedance output relative to the impedance input, so that the impedance at the amplifier output (114 and 120) is four times the input impedance. For an embodiment in which the second level is a quadrature power combiner (112), load reflections of the amplifier may be terminated at an isolation port (116 and 132). In addition, energy levels of the load reflections may be monitored (144).

Abstract translation: 功率放大器使用并行放大（102,104和106）和至少两级功率组合（108,110,112和118）来管理峰 - 峰电压摆动，从而降低电压击穿的可能性 个别晶体管。 每个级别的功率合成提供了一个向上的阻抗转换。 例如，两个功率级别的组合可以使阻抗输出相对于阻抗输入加倍，使得放大器输出（114和120）处的阻抗是输入阻抗的四倍。 对于其中第二电平是正交功率组合器（112）的实施例，放大器的负载反射可以在隔离端口（116和132）处终止。 另外，可以监测负载反射的能量水平（144）。

公开(公告)号：WO2006014501B1

公开(公告)日：2006-09-14

申请号：PCT/US2005024009

申请日：2005-07-06

Applicant: AMALFI SEMICONDUCTOR INC ,  BURNS LAWRENCE M ,  WOO CHONG L

Inventor： BURNS LAWRENCE M ,  WOO CHONG L

IPC: H03F3/68

CPC classification number: H03F3/604 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/198 ,  H03F2200/435 ,  H03F2200/541 ,  H03F2203/45058

Abstract: A power amplifier uses parallel amplification (102, 104 and 106) and at least two levels of power combining (108, 110, 112 and 118) to manage peak-to-peak voltage swings, so as to reduce the likelihood of voltage breakdown at individual transistors. Each level of power combining provides an upward impedance transformation. For example, both levels of power combining may double the impedance output relative to the impedance input, so that the impedance at the amplifier output (114 and 120) is four times the input impedance. For an embodiment in which the second level is a quadrature power combiner (112), load reflections of the amplifier may be terminated at an isolation port (116 and 132). In addition, energy levels of the load reflections may be monitored (144).

Abstract translation: 功率放大器使用并联放大（102,104和106）和至少两个功率组合级（108,110,112和118）来管理峰 - 峰值电压摆幅，以减少电压击穿的可能性 单个晶体管。 每个级别的功率组合提供向上阻抗变换。 例如，两级功率组合可以使阻抗输出相对于阻抗输入增加一倍，使得放大器输出端（114和120）处的阻抗是输入阻抗的四倍。 对于其中第二电平是正交功率组合器（112）的实施例，放大器的负载反射可以在隔离端口（116和132）处终止。 另外，可以监视负载反射的能级（144）。

公开(公告)号：WO2006014465A2

公开(公告)日：2006-02-09

申请号：PCT/US2005/023905

申请日：2005-07-06

Applicant: AMALFI SEMICONDUCTOR, INC. ,  BURNS, Lawrence, M. ,  WOO, Chong, L. ,  SZETO, Clement

Inventor： BURNS, Lawrence, M. ,  WOO, Chong, L. ,  SZETO, Clement

IPC: H03F1/22

CPC classification number: H03F3/602 ,  H03F1/22 ,  H03F3/189 ,  H03F3/45188 ,  H03F2200/198 ,  H03F2200/541

Abstract: A power amplifier (10 and 58) utilizes cascode arrangements (34 and 36) to achieve target performance levels for a power amplifier, such as the type used in wireless communication devices. A negative resistance circuit is provided for the cascode arrangement such that high gain, or oscillation, is promoted during operation of the power amplifier. In one embodiment, the negative resistance circuit includes cross-coupling transistors (30 and 32). Various features are provided in order to reduce the susceptibility of the power amplifier to voltage breakdown while maintaining good performance.

Abstract translation: 功率放大器（10和58）利用共源共栅布置（34和36）来实现功率放大器（诸如无线通信设备中使用的类型）的目标性能水平。 为共源共栅布置提供负电阻电路，使得在功率放大器的操作期间促进高增益或振荡。 在一个实施例中，负阻电路包括交叉耦合晶体管（30和32）。 提供各种功能以降低功率放大器对电压击穿的敏感性，同时保持良好的性能。

公开(公告)号：WO2006014465A3

公开(公告)日：2006-04-06

申请号：PCT/US2005023905

申请日：2005-07-06

Applicant: AMALFI SEMICONDUCTOR INC ,  BURNS LAWRENCE M ,  WOO CHONG L ,  SZETO CLEMENT

Inventor： BURNS LAWRENCE M ,  WOO CHONG L ,  SZETO CLEMENT

IPC: H03F1/22 ,  H03F3/45

CPC classification number: H03F3/602 ,  H03F1/22 ,  H03F3/189 ,  H03F3/45188 ,  H03F2200/198 ,  H03F2200/541

Abstract: A power amplifier (10 and 58) utilizes cascode arrangements (34 and 36) to achieve target performance levels for a power amplifier, such as the type used in wireless communication devices. A negative resistance circuit is provided for the cascode arrangement such that high gain, or oscillation, is promoted during operation of the power amplifier. In one embodiment, the negative resistance circuit includes cross-coupling transistors (30 and 32). Various features are provided in order to reduce the susceptibility of the power amplifier to voltage breakdown while maintaining good performance.

Abstract translation: 功率放大器（10和58）利用共源共栅布置（34和36）来实现诸如无线通信设备中使用的类型的功率放大器的目标性能水平。 提供了用于共源共栅布置的负电阻电路，使得在功率放大器的操作期间促进高增益或振荡。 在一个实施例中，负电阻电路包括交叉耦合晶体管（30和32）。 提供各种特征以便降低功率放大器对电压击穿的敏感性，同时保持良好的性能。

公开(公告)号：WO2006014501A2

公开(公告)日：2006-02-09

申请号：PCT/US2005/024009

申请日：2005-07-06

Applicant: AMALFI SEMICONDUCTOR, INC. ,  BURNS, Lawrence, M. ,  WOO, Chong, L.

Inventor： BURNS, Lawrence, M. ,  WOO, Chong, L.

IPC: H03F3/68

CPC classification number: H03F3/604 ,  H03F3/211 ,  H03F3/45179 ,  H03F2200/198 ,  H03F2200/435 ,  H03F2200/541 ,  H03F2203/45058

Abstract: A power amplifier uses parallel amplification (102, 104 and 106) and at least two levels of power combining (108, 110, 112 and 118) to manage peak-to-peak voltage swings, so as to reduce the likelihood of voltage breakdown at individual transistors. Each level of power combining provides an upward impedance transformation. For example, both levels of power combining may double the impedance output relative to the impedance input, so that the impedance at the amplifier output (114 and 120) is four times the input impedance. For an embodiment in which the second level is a quadrature power combiner (112), load reflections of the amplifier may be terminated at an isolation port (116 and 132). In addition, energy levels of the load reflections may be monitored (144).

Abstract translation: 功率放大器使用并行放大（102,104和106）和至少两级功率组合（108,110,112和118）来管理峰间电压摆动，因此 以降低单个晶体管电压击穿的可能性。 每个级别的功率合成提供了一个向上的阻抗转换。 例如，两个功率级别的组合可以使阻抗输出相对于阻抗输入加倍，使得放大器输出（114和120）处的阻抗是输入阻抗的四倍。 对于其中第二电平是正交功率组合器（112）的实施例，放大器的负载反射可以在隔离端口（116和132）处终止。 另外，可以监测负载反射的能量水平（144）。