公开(公告)号：WO2012134560A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064486

申请日：2011-12-12

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  TOLL, Bret L. ,  VALENTINE, Robert C. ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  OULD-AHMED-VALL, Elmoustapha ,  BRADFORD, Dennis R. ,  WU, Lisa K.

Inventor： SAN ADRIAN, Jesus Corbal ,  TOLL, Bret L. ,  VALENTINE, Robert C. ,  WIEDEMEIER, Jeffrey G. ,  SAMUDRALA, Sridhar ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  OULD-AHMED-VALL, Elmoustapha ,  BRADFORD, Dennis R. ,  WU, Lisa K.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30192 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.

Abstract translation: 描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。 在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的 数据元素到达目的地的目标位置。

公开(公告)号：WO2013095511A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066854

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  CORBAL, Jesus ,  WU, Lisa, K. ,  CHRYSOS, George, Z. ,  FORSYTH, Andrew, T. ,  SUNDARARAMAN, Ramacharan Charan

Inventor： CORBAL, Jesus ,  WU, Lisa, K. ,  CHRYSOS, George, Z. ,  FORSYTH, Andrew, T. ,  SUNDARARAMAN, Ramacharan Charan

IPC: G06F15/80 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0815 ,  G06F9/30047 ,  G06F12/0811 ,  G06F12/0862

Abstract: A method performed by a processor is described. The method includes executing an instruction. The instruction has an address as an operand. The executing of the instruction includes sending a signal to cache coherence protocol logic of the processor. In response to the signal, the cache coherence protocol logic issues a request for ownership of a cache line at the address. The cache line is not in a cache of the processor. The request for ownership also indicates that the cache line is not to be sent to the processor.

Abstract translation: 描述由处理器执行的方法。 该方法包括执行指令。 该指令具有作为操作数的地址。 指令的执行包括向处理器的高速缓存一致性协议逻辑发送信号。 响应于该信号，高速缓存一致性协议逻辑在地址处发出对高速缓存行的所有权的请求。 高速缓存行不在处理器的高速缓存中。 所有权请求也表示高速缓存行不被发送到处理器。

公开(公告)号：WO2013089791A1

公开(公告)日：2013-06-20

申请号：PCT/US2011/065635

申请日：2011-12-16

Applicant: INTEL CORPORATION ,  CORBAL, Jesus ,  FORSYTH, Andrew T. ,  WU, Lisa K. ,  FLETCHER, Thomas D.

Inventor： CORBAL, Jesus ,  FORSYTH, Andrew T. ,  WU, Lisa K. ,  FLETCHER, Thomas D.

IPC: G06F9/30 ,  G06F9/305 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3836 ,  G06F15/8053 ,  G06F17/17 ,  G06T3/4007

Abstract: Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

Abstract translation: 指令和逻辑提供矢量线性插值功能。 在一些实施例中，响应于指令指定：来自一组向量寄存器的第一操作数，每个向量元素的大小，用于计算线性内插的向量元素的一部分，来自一组向量的第二操作数 寄存器和第三操作数; 执行单元分别从第一，第二和第三操作数中的对应数据字段读取向量元素的大小的第一值，第二和第三值，并计算内插值作为第一值乘以第二值减去 第二个值乘以第三个值加上第三个值。

公开(公告)号：WO2012135494A2

公开(公告)日：2012-10-04

申请号：PCT/US2012/031202

申请日：2012-03-29

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  GIRKAR, Milind Baburao ,  WU, Lisa K. ,  BRADFORD, Dennis R. ,  LEE, Victor W.

Inventor： SAN ADRIAN, Jesus Corbal ,  SANS, Roger Espasa ,  GIRKAR, Milind Baburao ,  WU, Lisa K. ,  BRADFORD, Dennis R. ,  LEE, Victor W.

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30192

Abstract: Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.

Abstract translation: 描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。 在一些实施例中，对齐指令的执行导致将两个级联源的数据元素的选择性存储存储在目的地中。

公开(公告)号：WO2012134561A1

公开(公告)日：2012-10-04

申请号：PCT/US2011/064487

申请日：2011-12-12

Applicant: INTEL CORPORATION ,  SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

Inventor： SAN ADRIAN, Jesus Corbal ,  TOLL, Bret ,  VALENTINE, Robert C. ,  GIRKAR, Milind Baburao ,  FORSYTH, Andrew Thomas ,  CHRYSOS, George Z. ,  GROCHOWSKI, Edward Thomas ,  BRADFORD, Dennis ,  WU, Lisa, K. ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/324 ,  G06F9/30018 ,  G06F9/30058 ,  G06F9/30094

Abstract: Embodiments of systems, apparatuses, and methods for performing a jump instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a conditional jump to an address of a target instruction when all of bits of a writemask are zero, wherein the address of the target instruction is calculated using an instruction pointer of the instruction and the relative offset.

Abstract translation: 描述了用于在计算机处理器中执行跳转指令的系统，装置和方法的实施例。 在一些实施例中，当写入掩码的所有位都为零时，混合指令的执行导致到目标指令的地址的条件跳转，其中使用指令的指令指针和相对值计算目标指令的地址 抵消。

公开(公告)号：WO2013095619A1

公开(公告)日：2013-06-27

申请号：PCT/US2011067096

申请日：2011-12-23

Applicant: INTEL CORP ,  CORBAL JESUS ,  FORSYTH ANDREW T ,  FLETCHER THOMAS D ,  WU LISA K ,  SPRANGLE ERIC

Inventor： CORBAL JESUS ,  FORSYTH ANDREW T ,  FLETCHER THOMAS D ,  WU LISA K ,  SPRANGLE ERIC

IPC: G06F9/30 ,  G06F9/302

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3893

Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand)) + (b*(second vector operand)) + c.

Abstract translation: 描述了具有执行单元逻辑电路的处理核心，该执行单元逻辑电路具有存储第一向量输入操作数的第一寄存器，存储第二向量输入操作数的第二寄存器以及存储包含标量输入操作数a，b的打包数据结构的第三寄存器 ， C。 执行单元逻辑电路还包括执行操作（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c的乘法器。

公开(公告)号：WO2013095619A9

公开(公告)日：2013-06-27

申请号：PCT/US2011/067096

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  CORBAL, Jesus ,  FORSYTH, Andrew T. ,  FLETCHER, Thomas D. ,  WU, Lisa K. ,  SPRANGLE, Eric

Inventor： CORBAL, Jesus ,  FORSYTH, Andrew T. ,  FLETCHER, Thomas D. ,  WU, Lisa K. ,  SPRANGLE, Eric

IPC: G06F9/30 ,  G06F9/302

Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand)) + (b*(second vector operand)) + c.

公开(公告)号：WO2012135494A3

公开(公告)日：2012-12-27

申请号：PCT/US2012031202

申请日：2012-03-29

Applicant: INTEL CORP ,  SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  GIRKAR MILIND BABURAO ,  WU LISA K ,  BRADFORD DENNIS R ,  LEE VICTOR W

Inventor： SAN ADRIAN JESUS CORBAL ,  SANS ROGER ESPASA ,  GIRKAR MILIND BABURAO ,  WU LISA K ,  BRADFORD DENNIS R ,  LEE VICTOR W

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30192

Abstract: Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.

Abstract translation: 描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。 在一些实施例中，对齐指令的执行导致将两个连接的源的数据元素的选择性存储存储在目的地中。