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    INSTRUCTION FOR MERGING MASK PATTERNS
    5.
    发明申请
    INSTRUCTION FOR MERGING MASK PATTERNS 审中-公开
    指纹拼接图案

    公开(公告)号：WO2013095635A1

    公开(公告)日：2013-06-27

    申请号：PCT/US2011/067199

    申请日：2011-12-23

    Applicant: INTEL CORPORATION ,  CORBAL, Jesus ,  CRAIGHEAD, Matthew, J. ,  BRADFORD, Dennis, R. ,  HALL, Jonathan, C. ,  FORSYTH, Andrew, T.

    Inventor： CORBAL, Jesus ,  CRAIGHEAD, Matthew, J. ,  BRADFORD, Dennis, R. ,  HALL, Jonathan, C. ,  FORSYTH, Andrew, T.

    IPC: G06F9/30 ,  G06F9/305 ,  G06F9/38

    CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

    Abstract: A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.

    Abstract translation: 描述了一种包括获取指令并解码指令的方法。 该方法还包括从由该指令识别的第一屏蔽寄存器空间位置获取第一屏蔽矢量。 该方法还包括从由该指令识别的第二屏蔽寄存器空间位置获取第二屏蔽矢量。 该方法还包括通过将第一和第二屏蔽矢量合并为单个数据结构并使单个数据结构被写入由该指令识别的存储器位置来执行该指令。

    PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS
    8.
    发明申请
    PROCESSORS HAVING FULLY-CONNECTED INTERCONNECTS SHARED BY VECTOR CONFLICT INSTRUCTIONS AND PERMUTE INSTRUCTIONS 审中-公开
    具有由VECTOR CONFLICT指令和指令说明共享的完全连接的互连的处理程序

    公开(公告)号：WO2013101132A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067982

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

    Inventor： FORSYTH, Andrew Thomas ,  BRADFORD, Dennis R.

    IPC: G06F13/14 ,  G06F9/30 ,  G06F9/305

    CPC classification number: G06F9/30036 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/3818 ,  G06F9/3838

    Abstract: An apparatus includes a decode unit to decode a permute instruction and a vector conflict instruction. A vector execution unit is coupled with the decode unit and includes a fully-connected interconnect. The fully-connected interconnect has at least four inputs to receive at least four corresponding data elements of at least one source vector. The fully-connected interconnect has at least four outputs. Each of the at least four inputs is coupled with each of the at least four outputs. The execution unit also includes a permute instruction execution logic coupled with the at least four outputs and operable to store a first vector result in response to the permute instruction. The execution unit also includes a vector conflict instruction execution logic coupled with the at least four outputs and operable to store a second vector result in a destination storage location in response to the vector conflict instruction.

    Abstract translation: 一种装置包括解码单元，用于解码置换指令和向量冲突指令。 向量执行单元与解码单元耦合并且包括完全连接的互连。 完全连接的互连具有至少四个输入以接收至少一个源向量的至少四个对应的数据元素。 完全连接的互连至少有四个输出。 所述至少四个输入中的每一个与所述至少四个输出中的每一个耦合。 所述执行单元还包括与所述至少四个输出耦合的置换指令执行逻辑，并且可操作以响应于所述置换指令来存储第一向量结果。 执行单元还包括与至少四个输出耦合的向量冲突指令执行逻辑，并且可操作以响应于向量冲突指令将第二向量结果存储在目的地存储位置中。

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