公开(公告)号：WO1998023069A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021467

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Abstract translation: 一种使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差的相位检测器。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈回路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较，以产生两个数字信号：接收信号的同相（I）和正交相位（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减少I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差并构造与该差成比例的相位误差信号来确定相位误差信号的大小。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

公开(公告)号：WO1998023036A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021367

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  SCHNIZLEIN, Paul ,  BELL, Ed

IPC: H03L07/14

CPC classification number: H04L27/22 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/146 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/2273 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers start to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time. By thus anticipating the frequency of the carrier, this carrier-recovery loop can have an improved acquisition time to reach phase lock. The initialization value of the feedback signal can be generated by recording a sample of the feedback signal when the carrier-recovery loop is phase-locked to a received signal or to an on-board crystal oscillator. The invention also includes a mechanism to correct drifts in the crystal oscillator's frequency.

Abstract translation: 具有促进循环初始化的特征的通信系统中的接收机的载波恢复回路。 载波恢复环路是使用反馈信号将恢复振荡器锁相到接收信号的载波的PLL。 在本发明中，将反馈信号的初始化值存储在存储器中并提供给数字控制的恢复振荡器（DCO）。 该初始化值使恢复的信号达到近似载波频率的初始频率。 当接收机开始与载波获取锁相时，载波恢复环路处于接近期望相位锁的状态。 以这种方式准备DCO对载体恢复循环有显着的改进。 环路获取锁相的响应时间部分取决于其与载波的初始频率偏移。 一般来说，减少初始偏移可以减少环路的采集时间。 通过这样预期载波的频率，该载波恢复回路可以具有改善的采集时间以达到锁相。 反馈信号的初始化值可以通过当载波恢复回路被锁相到接收信号时记录反馈信号的样本，或通过记录在板上的晶体振荡器来产生。 本发明还包括校正晶体振荡器频率漂移的机制。

公开(公告)号：WO1998023071A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021469

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  SCHINZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A digital loop filter in the carrier-recovery loop of a digital communications receiver. The recovery loop is a PLL that keeps the receiver oscillator locked to the carrier wave, and the loop filter provides control over the PLL's frequency response by conditioning an error signal that is fed back to the receiver oscillator. In the present invention, the error signal is a digital signal, and the loop filter is implemented in digital hardward. With this implementation the characteristics of the loop filter are determined by logic design rather than by physical features of analog components, thereby giving this filter a more precise function than one with analog integrators. This implementation is also immune to the low tolerances typical of the manufacturing process for analog devices (especially on monolithic circuits), and is more easily adjusted than its analog counterparts. Two gain coefficients characterize the loop filter in the present invention. These gain coefficients are chosen to be powers of two, simplifying the process of multiplying them with the digital error signal. The gain coefficients are read from a memory, making the loop filter easily programmable. By changing the gain coefficients during operation of the receiver, the carrier-recovery loop can be placed in one of the several operating modes, including acquisition, tracking, and hold. The receiver can be configured with the appropriate values of the gain coefficients for each operating mode during the initial assembly and during subsequent reconfigurations.

Abstract translation: 数字通信接收机的载波恢复回路中的数字环路滤波器。 恢复环路是将接收器振荡器锁定到载波的PLL，环路滤波器通过调节反馈到接收机振荡器的误差信号来提供对PLL频率响应的控制。 在本发明中，误差信号是数字信号，环路滤波器以数字硬件方式实现。 通过这种实现，环路滤波器的特性由逻辑设计而不是模拟组件的物理特性决定，从而使得该滤波器比具有模拟积分器的功能更精确。 该实现也不受模拟器件（特别是单片电路）的制造工艺典型的低容差的影响，并且比其模拟器件更容易调整。 两个增益系数表征本发明中的环路滤波器。 这些增益系数被选为2的幂，简化了与数字误差信号相乘的过程。 从存储器读取增益系数，使得环路滤波器易于编程。 通过在接收机操作期间改变增益系数，载波恢复回路可以放置在几种操作模式之一，包括采集，跟踪和保持。 可以在初始组装期间和随后的重新配置期间，为每个操作模式的接收机配置适当的增益系数值。