公开(公告)号：WO2006078860A8

公开(公告)日：2007-08-09

申请号：PCT/US2006001969

申请日：2006-01-19

Applicant: MARVELL WORLD TRADE LTD

Inventor： WANG CINDY CHUN ,  XU XIANGYANG SIMON ,  CHEN XIAOCHU

IPC: H04B1/69

CPC classification number: H04L27/22 ,  H03K2005/00241 ,  H04L27/2275 ,  H04L2025/03401 ,  H04L2027/0046 ,  H04L2027/0063

Abstract: A delay buffer includes a first shift register (50) receiving input data and having a shift signal input port. The first shift register right shifts the input data responsive to a shift signal on the shift signal input port. The shift signal is determined based on an effective bit width of the input data. A first delay line (56) receives the shifted data from the first shift register while a second delay line (58) of equal length to the first delay line receives the shift signal. A second shift register (60) receives the output from the first delay line and receives the output of the second delay line on a shift signal input port (62). The second shift register then left shifts the data contained therein according to the shift signal.

Abstract translation: 延迟缓冲器包括接收输入数据并具有移位信号输入端口的第一移位寄存器（50）。 第一移位寄存器根据移位信号输入端口上的移位信号，右移位输入数据。 基于输入数据的有效位宽来确定移位信号。 第一延迟线（56）从第一移位寄存器接收移位的数据，而与第一延迟线等长的第二延迟线（58）接收移位信号。 第二移位寄存器（60）接收来自第一延迟线的输出，并接收移位信号输入端口（62）上的第二延迟线的输出。 然后，第二移位寄存器根据移位信号移位其中包含的数据。

公开(公告)号：WO2007016219A1

公开(公告)日：2007-02-08

申请号：PCT/US2006/029141

申请日：2006-07-28

Applicant: ITT MANUFACTURING ENTERPRISES, INC. ,  RASMUSSEN, Donald, John

Inventor： RASMUSSEN, Donald, John

IPC: H04L27/227 ,  H04B1/707

CPC classification number: H04B1/7085 ,  H04L27/2275

Abstract: A method of correcting phase error of a phase shift keyed (PSK) signal includes (a) receiving a signal modulated by a spreading sequence; (b) despreading the received signal using a receiver spreading sequence similar to the spreading sequence of step (a); (c) calculating a crosscorrelation profile between the receiver spreading sequence and the received signal; and (d) calculating an autocorrelation profile of the receiver spreading sequence to determine a spreading code property (SCP). The method also includes (e) estimating a timing error in alignment between the autocorrelation and the crosscorrelation profiles; and (f) correcting a phase error of the signal despread in step (c), by using the SCP and the estimated timing error.

Abstract translation: 校正相移键控（PSK）信号的相位误差的方法包括：（a）接收由扩展序列调制的信号; （b）使用类似于步骤（a）的扩展序列的接收机扩展序列解扩接收信号; （c）计算接收机扩展序列与接收信号之间的互相关分布; 和（d）计算接收机扩展序列的自相关分布以确定扩展码属性（SCP）。 该方法还包括（e）估计自相关和互相关分布之间的对准的定时误差; 以及（f）通过使用SCP和估计的定时误差来校正在步骤（c）中解扩的信号的相位误差。

公开(公告)号：WO2017165006A2

公开(公告)日：2017-09-28

申请号：PCT/US2017/017013

申请日：2017-02-08

Applicant: INTEL CORPORATION

Inventor： DA SILVA, Claudio ,  LEE, Wook Bong

CPC classification number: H04W72/0446 ,  H04L5/0048 ,  H04L27/2275 ,  H04L27/26 ,  H04L27/2613 ,  H04L27/2646 ,  H04L27/3827 ,  H04W72/0413 ,  H04W72/085

Abstract: Embodiments of an access point (AP), station (STA) and method for communication in accordance with frame formats of varying sizes of pilot portions are generally described herein. The AP may transmit, to the STA, a first downlink frame in accordance with a first downlink frame format. The AP may receive, from the STA, a phase noise measurement of the STA. The AP may select, based at least partly on the received phase noise measurement, a downlink frame format to enable a phase noise compensation at the STA. The AP may generate a downlink frame in accordance with the second downlink frame format, and may transmit the second downlink frame to the STA. In some cases, the first and second downlink frame formats may be based on different ratios of pilot portions to data portions.

Abstract translation: 根据导频部分的不同大小的帧格式进行通信的接入点（AP），站（STA）和方法的实施例在本文中一般性地被描述。 AP可以根据第一下行链路帧格式向STA发送第一下行链路帧。 AP可以从STA接收STA的相位噪声测量。 至少部分地基于接收到的相位噪声测量，AP可以选择下行链路帧格式以在STA处启用相位噪声补偿。 AP可以根据第二下行链路帧格式生成下行链路帧，并且可以将第二下行链路帧发送到STA。 在一些情况下，第一和第二下行链路帧格式可以基于导频部分与数据部分的不同比例。

公开(公告)号：WO2017059783A1

公开(公告)日：2017-04-13

申请号：PCT/CN2016/100836

申请日：2016-09-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： ZAMANI, Mahdi ,  NAJAFI, Hossein ,  YAO, Demin ,  MITRA, Jeebak ,  LI, Chuandong ,  ZHANG, Zhuhong

IPC: H04L27/00

CPC classification number: H04L25/03273 ,  H04L25/03203 ,  H04L27/0014 ,  H04L27/2275 ,  H04L27/3836 ,  H04L2027/0038

Abstract: A method and apparatus for performing residual phase noise compensation is described. A coarse carrier compensation of a received modulated signal is performed to obtain a coarse carrier compensated signal and a trellis-based residual carrier recovery is performed to estimate a residual phase noise of the coarse carrier compensated signal. The coarse carrier compensated signal is compensated based on the estimated residual phase noise.

Abstract translation: 描述了执行剩余相位噪声补偿的方法和装置。 执行接收的调制信号的粗略载波补偿以获得粗略的载波补偿信号，并且执行基于网格的残余载波恢复以估计粗略载波补偿信号的残余相位噪声。 基于估计的残余相位噪声来补偿粗略载波补偿信号。

公开(公告)号：WO1998023069A1

公开(公告)日：1998-05-28

申请号：PCT/US1997021467

申请日：1997-11-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  JANESCH, Stephen, T. ,  HENDRICKSON, Alan ,  SCHNIZLEIN, Paul

IPC: H04L27/227

CPC classification number: H04L27/2275 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L7/146 ,  H04B1/707 ,  H04L1/24 ,  H04L7/0334 ,  H04L27/22 ,  H04L27/2273 ,  H04L27/2277 ,  H04L2027/0028 ,  H04L2027/0046 ,  H04L2027/0067 ,  H04L2027/0069

Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Abstract translation: 一种使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差的相位检测器。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈回路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较，以产生两个数字信号：接收信号的同相（I）和正交相位（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减少I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差并构造与该差成比例的相位误差信号来确定相位误差信号的大小。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。

公开(公告)号：WO1996020539A1

公开(公告)日：1996-07-04

申请号：PCT/SE1995001546

申请日：1995-12-19

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (publ)

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON (publ) ,  LINDQUIST, Björn ,  ISBERG, Martin ,  WENDELRUP, Heino ,  SALLENHAG, Martin ,  GUSTAFSSON, Kjell

IPC: H04B01/10

CPC classification number: H03D3/009 ,  H04B1/30 ,  H04L27/2275 ,  H04L27/2332

Abstract: A digitally compensated direct-conversion receiver includes devices for generating digital samples of a base-band in-phase signal and a base-band quadrature signal and for detecting the presence of a second-order product signal produced by an amplitude-modulated interfering signal. Also, the apparatus comprises a device for digitally compensating the digital samples by removing the second-order product signal, thereby producing compensated digital samples. In one method of digitally compensating samples of an information signal quadrature-modulating a carrier signal, estimated samples of a second-order product from a switched carrier signal are formed by averaging the digital samples during two time periods and by determining a time of ramps in the in-phase and quadrature signals that occur between the time periods due to the interfering signal. The digital samples may be differentiated and the results smoothed in determining the time of the ramps. In another apparatus, the estimated samples of the second-order product signal are produced by a device for averaging a square of a difference between respective digital samples of the in-phase signal and the quadrature signal, thereby determining an amplitude of the amplitude-modulated carrier signal, and a device for combining the amplitude and the digital samples, thereby generating the estimated samples.

Abstract translation: 数字补偿直接转换接收机包括用于产生基带同相信号和基带正交信号的数字样本的装置，并用于检测由幅度调制干扰信号产生的二阶乘积信号的存在。 此外，该装置包括一个用于通过去除二阶乘积信号对数字样本进行数字补偿从而产生经补偿的数字样本的装置。 在对对载波信号进行正交调制的信息信号的样本进行数字补偿的一种方法中，通过在两个时间段期间对数字样本进行平均并且通过确定在两个时间段内的斜坡时间来形成来自切换载波信号的二阶乘积的估计样本 由于干扰信号在时间周期之间发生的同相和正交信号。 可以区分数字样本，并且在确定斜坡的时间时平滑结果。 在另一装置中，二阶乘积信号的估计样本由用于对同相信号和正交信号的相应数字样本之间的差的平方进行平均的装置产生，由此确定幅度调制的幅度 载波信号和用于组合幅度和数字样本的装置，由此产生估计样本。

公开(公告)号：WO1995015639A1

公开(公告)日：1995-06-08

申请号：PCT/US1994012280

申请日：1994-10-25

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  LOVE, Robert, Tristan ,  STEWART, Kenneth, A. ,  RAPALA, Bryan

IPC: H04L27/30

CPC classification number: H04L27/2275 ,  H04B1/707

Abstract: The present invention provides a downconverter method and apparatus for downconverting a multiphase modulated signal. The downconverter can be implemented in a multi-phase receiver such as a quadrature receiver. An analog-to-digital converter (103) converts an intermediate frequency signal to a digital signal at a sampling rate. A Hilbert transformation filter (104) and a delay element (105) connected in parallel provide respective passband quadrature and in-phase components of the digital signal. A digital translator (107) alters the passband quadrature and in-phase components based on a predetermined pattern to provide a baseband quadrature signal and a baseband in-phase signal. The digital translator (107) can be a pseudorandom sequence demodulator for demodulating a code division multiple access (CDMA) signal. Various types of DC estimation can also be provided in addition to automatic gain control.

Abstract translation: 本发明提供一种用于下变频多相位调制信号的下变频器方法和装置。 下变频器可以在诸如正交接收机的多相接收机中实现。 模数转换器（103）以采样速率将中频信号转换为数字信号。 并联连接的希尔伯特变换滤波器（104）和延迟元件（105）提供数字信号的各个通带正交和同相分量。 数字转换器（107）基于预定模式改变通带正交和同相分量，以提供基带正交信号和基带同相信号。 数字转换器（107）可以是用于解码码分多址（CDMA）信号的伪随机序列解调器。 除了自动增益控制之外，还可以提供各种类型的直流估计。

公开(公告)号：WO1982003736A1

公开(公告)日：1982-10-28

申请号：PCT/GB1979000113

申请日：1979-07-05

Applicant: WRIGHT SIMON CHARLES MARCUS

IPC: H03B03/04

CPC classification number: H04L7/0331 ,  H03L7/0992 ,  H04L27/2275

Abstract: Circuit permettant de synchroniser un signal avec la temporisation d'un signal donne, ce circuit comprenant: de multiples etages de comptage numerique (16, 17) disposes sous forme de diviseurs de frequence afin de produire une sortie divisee en frequence a partir d'une entree de frequence, le facteur de division du diviseur de frequence etant reglable a l'une quelconque de deux valeurs au moins, l'une des deux etages de comptage etant un circuit de division par deux dispose de facon a produire ledit signal de sortie; des moyens de comparaison de temps (5) permettant d'effectuer des comparaisons repetees de la temporisation de la sortie du diviseur de frequence avec celle d'un signal de reference, et de produire pour chaque comparaison un premier signal si la sortie precede la reference et un second signal si cette sortie est en retard par rapport a la reference, lesdits moyens de comparaison comprenant un premier circuit bi-stable (5) du type D et un circuit detecteur de transition (3, 4), la sortie de ce dernier circuit etant connectee a l'entree HORLOGE du circuit bi-stable, et l'entree D du circuit bi-stable etant connectee de facon a recevoir la meme entree que ledit circuit de division par deux appartenant au diviseur de frequence; des moyens d'integration (10, 11) connectes a la sortie des moyens de comparaison de temps et permettant d'integrer le premier signal dans un sens et le second signal dans le sens oppose; et des moyens de reglage du facteur de division (12) permettant de regler le facteur de division a une premiere valeur plus elevee si la valeur integree depasse un seuil dans le sens considere, et a une deuxieme valeur, plus basse, si la valeur integree depasse le seuil dans le sens oppose.

公开(公告)号：WO1980002631A1

公开(公告)日：1980-11-27

申请号：PCT/SE1980000034

申请日：1980-02-04

Applicant: DIANTEK HB ,  THERN R ,  RUUS J

Inventor： DIANTEK HB

IPC: H04Q09/00

CPC classification number: H04L27/1563 ,  H04B3/44 ,  H04L5/143 ,  H04L27/2092 ,  H04L27/2275 ,  H04Q9/14

Abstract: A data transmission arrangement for bi-directional transmission of bit-sequences between a central unit (CCU) and a plurality of terminal units (TU1, TU2, ...) is provided which is particularly adapted for data acquisition and feedback signaling of messages, and for process control. In the arrangement the data transmission can occur simultaneously with the power supply of the terminal units over a two-lead cable (L), to which a large number of terminal units can be connected in parallel. The method of operation of the arrangement permits an advantageously simple construction of the transmission and reception equipment in the central unit and the terminal units.

Abstract translation: 提供了一种用于在中央单元（CCU）和多个终端单元（TU1，TU2，...）之间进行双向传输比特序列的数据传输装置，其特别适用于消息的数据采集和反馈信令， 并用于过程控制。 在该布置中，数据传输可以通过双引线电缆（L）与终端单元的电源同时发生，并且多个终端单元可以并联连接到该双引线电缆。 该装置的操作方法允许在中央单元和终端单元中有利地简单地构造发射和接收设备。

公开(公告)号：WO2014187742A1

公开(公告)日：2014-11-27

申请号：PCT/EP2014/060084

申请日：2014-05-16

Applicant: ALCATEL LUCENT

Inventor： RAZZETTI, Luca, Gabriele ,  GAVIOLI, Giancarlo ,  PEPE, Marianna ,  COSTANTINI, Carlo

IPC: H04B10/61 ,  H04L27/00

CPC classification number: H04L27/2275 ,  H04B10/6165

Abstract: Embodiments relate to an apparatus (100; 300; 400; 500; 600) for recovering a phase of a received signal (S in ) carrying pilot and information symbols, wherein the received signal has been transmitted over a communication channel (200), the apparatus comprising a phase estimator (110) operable to determine a phase estimate (115) of a phase of the communication channel using the received signal, wherein the phase estimator (110) commits a phase slip with a phase slip probability (P s , Ρ τ ) depending on the communication channel (200); a demodulator (120) operable to determine demodulated pilot and information symbols (125) based on a coherent reception of the received pilot and information symbols using the determined phase estimate (115); a phase slip detector (130; 330; 430; 530; 630) operable to detect the phase slip based on a phase difference between at least one demodulated pilot symbol and at least one corresponding transmitted pilot symbol; and a phase corrector (140; 340; 440; 540) operable to correct a phase of demodulated information symbols based on the detected phase slip.

Abstract translation: 实施例涉及用于恢复携带导频和信息符号的接收信号（Sin）的相位的装置（100; 300; 400; 500; 600），其中所接收的信号已经通过通信信道（200）发送， 包括相位估计器（110），其可操作以使用所述接收信号确定所述通信信道的相位的相位估计（115），其中所述相位估计器（110）提交具有相位滑移概率（Ps，＆Rgr;τ ）取决于通信信道（200）; 解调器（120），用于基于使用所确定的相位估计（115）的所接收的导频和信息符号的相干接收来确定解调的导频和信息符号（125）; 相位滑动检测器（130; 330; 430; 530; 630），其可操作以基于至少一个解调的导频符号与至少一个对应的传输导频符号之间的相位差来检测相位滑移; 以及相位校正器（140; 340; 440; 540），其可操作以基于检测到的相位差来校正解调信息符号的相位。