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    MANAGING FREQUENCY CHANGES OF CLOCK SIGNALS ACROSS DIFFERENT CLOCK DOMAINS
    4.
    发明申请
    MANAGING FREQUENCY CHANGES OF CLOCK SIGNALS ACROSS DIFFERENT CLOCK DOMAINS 审中-公开
    管理不同时钟域的时钟信号频率变化

    公开(公告)号：WO2018013155A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2016/051813

    申请日：2016-09-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： KOMMRUSCH, Steven ,  MEHRA, Amitabh ,  BORN, Richard Martin

    IPC: G06F1/08 ,  G06F1/10

    Abstract: A processor (100) maintains a minimum setup time for data being transferred between clock domains (102, 103), including maintaining the minimum setup time in response to a frequency change in a clock signal for at least one of the clock domains. The processor employs one or more control modules (122, 124) that monitor clock edges in each of the clock domains to ensure that data is not accessed by the receiving clock domain from a storage location until a minimum number of phases have elapsed in the transferring clock domain after the data has been written to the storage location. Further, the control module maintains the minimum setup time in response to a change in clock frequency at one or both of the clock domains.

    Abstract translation: 处理器（100）维持用于在时钟域（102,103）之间传送的数据的最小建立时间，包括响应于时钟信号中的频率变化维持最小建立时间至少 其中一个时钟域。 处理器采用监视每个时钟域中的时钟边沿的一个或多个控制模块（122,124），以确保数据不被接收时钟域从存储位置访问，直到在传送中经过最小数量的阶段 数据写入存储位置之后的时钟域。 此外，响应于一个或两个时钟域处的时钟频率的变化，控制模块维持最小建立时间。

    ONBOARD MONITORING OF VOLTAGE LEVELS AND DROOP EVENTS
    6.
    发明申请
    ONBOARD MONITORING OF VOLTAGE LEVELS AND DROOP EVENTS 审中-公开

    公开(公告)号：WO2019168944A1

    公开(公告)日：2019-09-06

    申请号：PCT/US2019/019783

    申请日：2019-02-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： MEHRA, Amitabh ,  LEWIS, Dana G.

    IPC: G06F1/32 ,  G01R19/255 ,  G01R19/00

    Abstract: A processor [100] includes a plurality of voltage droop detectors [130] positioned at multiple points of the processor. The detectors monitor voltage levels and alerts the processor if a droop event has been detected in real time. Multiple droops can be detected simultaneously, with each detected droop event generating an alert that is sent to a processor module, such as a clock control module, to act based on the detected droop. Each detector employs a ring oscillator [206] that generates a periodic signal and a corresponding count based on that signal, where the frequency of the signal varies based on a voltage at the corresponding point being monitored.

    PSEUDO-RANDOM LOGICAL TO PHYSICAL CORE ASSIGNMENT AT BOOT FOR AGE AVERAGING
    7.
    发明申请
    PSEUDO-RANDOM LOGICAL TO PHYSICAL CORE ASSIGNMENT AT BOOT FOR AGE AVERAGING 审中-公开

    公开(公告)号：WO2019125569A1

    公开(公告)日：2019-06-27

    申请号：PCT/US2018/052456

    申请日：2018-09-24

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： MEHRA, Amitabh ,  BERNUCHO, Krishna Sai

    IPC: G06F9/50

    CPC classification number: G06F9/4408 ,  G06F9/4403

    Abstract: A computing device (100) includes a processor (100) having a plurality of cores (111-114), a core translation component (616), and a core assignment component (617). The core translation component provides a set of registers (405), one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

    CLOCK ADJUSTMENT FOR VOLTAGE DROOP
    8.
    发明申请
    CLOCK ADJUSTMENT FOR VOLTAGE DROOP 审中-公开
    时钟调整电压跌落

    公开(公告)号：WO2018013156A1

    公开(公告)日：2018-01-18

    申请号：PCT/US2016/051814

    申请日：2016-09-15

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： KOMMRUSCH, Steven ,  MEHRA, Amitabh ,  BORN, Richard Martin ,  YOUNG, Bobby D.

    IPC: G06F11/07 ,  G06F11/30

    Abstract: A processor (100) adjusts frequencies of one or more clock signals (230) in response to a voltage droop at the processor. The processor generates at least one clock signal by generating a plurality of base clock signals (220, 221, 222, 223, 224, 225, 226, 227), each of the base clock signals having a common frequency but a different phase. The processor also generates a plurality of enable signals, wherein each enable signal governs whether a corresponding one of the base clock signals is used to generate the clock signal. The enable signals therefore determine the frequency of the clock signal. In response to detecting a voltage droop, the processor adjusts the enable signals used to generate the clock signal, thereby reducing the frequency of the clock signal droop.

    Abstract translation: 处理器（100）响应于处理器处的电压下垂来调整一个或多个时钟信号（230）的频率。 处理器通过产生多个基本时钟信号（220,221,222,223,224,225,226,227）来产生至少一个时钟信号，每个基本时钟信号具有共同的频率但是不同的相位。 处理器还产生多个使能信号，其中每个使能信号控制是否使用对应的一个基本时钟信号来产生时钟信号。 使能信号因此确定时钟信号的频率。 响应于检测到电压下降，处理器调整用于产生时钟信号的使能信号，从而降低时钟信号下垂的频率。

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