公开(公告)号：WO2017156360A1

公开(公告)日：2017-09-14

申请号：PCT/US2017/021725

申请日：2017-03-10

Applicant: ANALOG DEVICES, INC.

Inventor： FOLEY, David P.

IPC: H03K5/135 ,  H03K5/133

Abstract: An exemplary timing generator includes a coarse delay circuit configured to generate a coarse delayed rising edge signal and a coarse delayed falling edge signal from a reference timing signal; a fine delay circuit configured to generate a fine delayed rising edge signal from the coarse delayed rising edge signal and a fine delayed falling edge signal from the coarse delayed falling edge signal; an edge combiner configured to generate the timing signal based on the fine delayed rising edge signal and the fine delayed falling edge signal; and a masking circuit configured to generate a rising edge masking signal and a falling edge masking signal for controlling when the rising edges and the falling edges of the timing signal are generated.

Abstract translation: 示例性定时发生器包括：粗略延迟电路，其被配置为从参考定时信号生成粗略延迟上升沿信号和粗略延迟下降沿信号; 精细延迟电路，被配置为从所述粗略延迟上升沿信号和来自所述粗略延迟下降沿信号的精确延迟下降沿信号生成精细延迟上升沿信号; 边沿组合器，被配置为基于精延迟的上升沿信号和精延迟的下降沿信号来产生定时信号; 以及掩蔽电路，被配置为产生用于控制定时信号的上升沿和下降沿何时产生的上升沿掩蔽信号和下降沿掩蔽信号。