公开(公告)号：WO9107825A3

公开(公告)日：1991-06-27

申请号：PCT/US9006790

申请日：1990-11-19

Applicant: ANALOG DEVICES INC

Inventor： BROKAW A PAUL

IPC: H03M1/06 ,  H03M1/08 ,  H03M1/78

CPC classification number: H03M1/089 ,  H03M1/785

Abstract: A termination circuit for an R-2R ladder network for producing weighted currents, the 2R terminating resistor of the ladder being connected to an excitation source voltage which is 2(kT/q)ln2 closer to the supply voltage than the emitter of the current source in the last (i.e., least significant) leg of the ladder. The excitation source is fabricated with just one type of bipolar transistor and does not require an amplifier or frequency compensation capacitor(s). The excitation source is a simple circuit requiring only five transistors, at least one of which has an emitter area which is a multiple of the emitter areas of the current source transistors. The base-emitter voltages of the transistors in the excitation source are connected in a voltage loop that goes from a voltage VLSB at the emitter of the current source transistor connected to the least significant ladder network shunt resistor to a voltage, Vt, which would be equal to VLSB, if all six transistors in the loop had the same emitter area, but which deviates therefrom by 2(kT/q)ln2 due to the differences in the emitter areas.

Abstract translation: 用于产生加权电流的R-2R梯形网络的端接电路，梯形的2R终端电阻连接到比电流源的发射极更接近电源电压的2（kT / q）ln2的激励源电压 在阶梯的最后（即最不重要的）阶段。 激励源只用一种双极型晶体管制造，不需要放大器或频率补偿电容器。 激励源是一个简单的电路，只需要五个晶体管，其中至少一个晶体管的发射极面积是电流源晶体管发射极面积的倍数。 激励源中的晶体管的基极 - 发射极电压连接在电压回路中，该电压回路从连接到最低有效梯形网络分流电阻器的电流源晶体管的发射极处的电压VLSB变为电压Vt， 等于VLSB，如果回路中的所有六个晶体管具有相同的发射极面积，但由于发射极面积的差异，其偏离2（kT / q）ln2。

公开(公告)号：WO8904949A3

公开(公告)日：1989-11-02

申请号：PCT/US8803668

申请日：1988-10-19

Applicant: ANALOG DEVICES INC

Inventor： DEVITO LAWRENCE M ,  BROKAW A PAUL

IPC: G01D5/22 ,  G06G7/161

CPC classification number: G01D5/2266 ,  G01D5/2216 ,  G01D5/2291 ,  G06G7/161

Abstract: A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to the LVDT primary winding. The interface circuit further includes a decoder responsive to signals induced in the LVDT secondary windings for computing the position p of the LVDT core as a solution to the equation p= K(A-B)/(A+B), where A and B represent the signals induced in the primary winding and K is a constant scale factor. The decoder includes circuitry for rectifying and filtering the secondary signals, a charge balance loop responsive to the detected signals for providing a binary signal having a duty cycle representative of B/(A+B), and an output circuit responsive to the binary signal for providing the position output. The decoder provides excellent scale factor stability and linearity and is relatively insensitive to variations in primary drive amplitude.