公开(公告)号：WO2018009371A1

公开(公告)日：2018-01-11

申请号：PCT/US2017/039423

申请日：2017-06-27

申请人： APPLE INC.

发明人： KLASS, Edgardo F.

IPC分类号： G06F1/10 ,  G06F1/32 ,  H03K3/012

CPC分类号： H03K19/0016 ,  G06F1/10 ,  G06F1/3296 ,  H03K3/012 ,  H03K19/018521 ,  H03K19/17784 ,  Y02D10/172

摘要： In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.

摘要翻译： 在一个实施例中，集成电路包括由从时钟树电路接收的时钟计时的时钟树电路和逻辑电路。 逻辑电路由第一电源电压供电。 集成电路包括电压调节器，该电压调节器接收第一电源电压并且生成具有比第一电源电压的大小低预定量的大小的第二电源电压。 第二电源电压可以在使用期间随着动态变化追踪第一电源电压，无论是有意改变到工作状态还是噪声引起的变化。 第二电源电压可以用于为时钟树的至少一部分供电。