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公开(公告)号：WO2023285647A1
公开(公告)日：2023-01-19
申请号：PCT/EP2022/069841
申请日：2022-07-15
申请人： DOLPHIN DESIGN
发明人： LOUVAT, Mathieu , JACQUET, François
IPC分类号： H03K3/037 , H03K3/012 , H03K19/003 , G01R31/317
摘要： The present disclosure relates to a circuit comprising: - a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and - a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.
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公开(公告)号：WO2021040947A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/043915
申请日：2020-07-28
申请人： INTEL CORPORATION
发明人： SHAMANNA, Gururaj , GOYAL, Mitesh , SALAKA, Jagadeesh Chandra , NAYAK, Purna C. , SHARMA, Abhishek , SAHU, Harishankar
摘要： A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing oppurtunities. Swithcing power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.
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公开(公告)号：WO2020252452A1
公开(公告)日：2020-12-17
申请号：PCT/US2020/037737
申请日：2020-06-15
发明人： PETRY, Joseph , CARROLL, Brian M.
IPC分类号： H03K3/012 , H03K17/725 , H03K3/037 , G06F13/00
摘要： Methods, systems, and computer readable media described herein can be operable to facilitate transitioning a device from a first state to a second state. A switch described herein allows for the use of an electronic circuit to perform the toggle and persistence functions while simultaneously giving more flexibility to the industrial design and physical switch implementation. The switch allows this preserving of the state using only a toggle on a voltage and thus allowing for a hardware only solution. The switch described herein allows for the use of smaller and less complicated mechanical switches allowing for more compact industrial designs. The switch uses a programmable voltage reference as a 1 bit non-volatile memory cell that is programmed by means of a logic pulse to the device. This allows a software independent setting of the state of the privacy switch. This state will remain through power cycles.
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公开(公告)号：WO2019220123A1
公开(公告)日：2019-11-21
申请号：PCT/GB2019/051346
申请日：2019-05-16
发明人： DE OLIVEIRA, Joao
IPC分类号： H03K3/012 , H03K19/094 , H03K19/0944
摘要： An AND gate comprises:a first input;a second input;an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.
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公开(公告)号：WO2018009371A1
公开(公告)日：2018-01-11
申请号：PCT/US2017/039423
申请日：2017-06-27
申请人： APPLE INC.
发明人： KLASS, Edgardo F.
CPC分类号： H03K19/0016 , G06F1/10 , G06F1/3296 , H03K3/012 , H03K19/018521 , H03K19/17784 , Y02D10/172
摘要： In an embodiment, an integrated circuit includes a clock tree circuit and logic circuitry that is clocked by the clocks received from the clock tree circuit. The logic circuit is powered by a first power supply voltage. The integrated circuit includes a voltage regulator that receives the first power supply voltage and generates a second power supply voltage having a magnitude that is lower than the magnitude of the first power supply voltage by a predetermined amount. The second power supply voltage may track the first power supply voltage over dynamic changes during use, either intentional changes to operating state or noise-induced changes. The second power supply voltage may be used to power at least a portion of the clock tree.
摘要翻译： 在一个实施例中，集成电路包括由从时钟树电路接收的时钟计时的时钟树电路和逻辑电路。 逻辑电路由第一电源电压供电。 集成电路包括电压调节器，该电压调节器接收第一电源电压并且生成具有比第一电源电压的大小低预定量的大小的第二电源电压。 第二电源电压可以在使用期间随着动态变化追踪第一电源电压，无论是有意改变到工作状态还是噪声引起的变化。 第二电源电压可以用于为时钟树的至少一部分供电。
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公开(公告)号：WO2017151293A1
公开(公告)日：2017-09-08
申请号：PCT/US2017/017459
申请日：2017-02-10
IPC分类号： H03K3/012 , H03K3/3562
CPC分类号： H03K3/012 , H03K3/356104 , H03K3/35625
摘要： In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.
摘要翻译： 在一个示例中，该装置包括第一与门，第二与门，第一或非门，第二或非门，第三或非门，第一反相器和第二反相器。 第一与门输出耦合到第一或非门第一输入。 第一或非门输出端耦合到第二或非门第一输入端。 第二或非门输出耦合到第一或非门第二输入。 第一反相器输出端耦合到第一与门第二输入端和第二或非门第二输入端。 第二与门的第一输入端耦合到第一反相器输出端。 第三NOR门第一输入端连接到第二NOR门输出端。 第三或非门第二输入端耦合到第二与门输出端。 第二个反相器输出端连接到第二个与门第二个输入端。
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公开(公告)号：WO2017133466A1
公开(公告)日：2017-08-10
申请号：PCT/CN2017/071645
申请日：2017-01-19
申请人： 中国电子科技集团公司第二十四研究所
IPC分类号： H03K3/012
CPC分类号： H03K3/012
摘要： 一种高速低功耗触发器，包括控制信号生成电路、使能单元和锁存器结构，所述锁存器结构包括两输入端、两输出端、两使能端、第二使能端和接地端，所述使能单元包括两使能电路，所述控制信号生成电路的输出信号X和外部控制信号D作为第一使能电路的输入信号，所述第一使能电路的输出端与第一使能端连接，所述控制信号生成电路的输出信号X和外部控制信号D的反相信号DB作为第二使能电路的输入信号，所述第二使能电路的输出端与第二使能端连接；该触发器结构和传统结构相比，电路结构简单，并且锁存器的输出端寄生电容很小，提高了触发器的速度，并且没有静态功耗。
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公开(公告)号：WO2016190956A1
公开(公告)日：2016-12-01
申请号：PCT/US2016/025180
申请日：2016-03-31
发明人： YE, Qi , DILLEN, Steven James , DATTA, Animesh , DUAN, Zhengyu , SAHU, Satyanarayana , NARENDRANATH, Praveen
CPC分类号： H03K3/0375 , H03K3/012 , H03K3/037 , H03K5/131
摘要： A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally (Formula (A) at a delay module output, where I 1 is a function of I and I A is a function of I N 0 and B 0, and where I is a delay module input, B 0 is a first input bit, and I N0 is a first net input.
摘要翻译： 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在功能上提供（延迟模块输出中的公式（A）），其中I 1是I的函数，IA是IN 0和B0的函数，其中I是延迟模块输入，B0是第一个输入位 ，而N0是第一个净输入。
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公开(公告)号：WO2015138851A1
公开(公告)日：2015-09-17
申请号：PCT/US2015/020368
申请日：2015-03-13
发明人： PHAM, Ha, M. , SHIN, Jin-Uk
CPC分类号： H03K3/356156 , G06F1/04 , G06F1/3237 , H03K3/012 , Y02D10/128
摘要： Embodiments of a flip-flip circuit are disclosed that may allow a reduction in data setup time and lower switching power. The flip-flop circuit may include an input circuit, an output circuit, a clock circuit, and a feedback circuit. The clock circuit may be operable to generate internal clocks dependent upon received data, and the generated internal clocks may enable the feedback and input circuits.
摘要翻译： 公开了可以减少数据建立时间和降低开关功率的触发器电路的实施例。 触发器电路可以包括输入电路，输出电路，时钟电路和反馈电路。 时钟电路可以用于根据接收到的数据产生内部时钟，并且所产生的内部时钟可以使反馈和输入电路成为可能。
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公开(公告)号：WO2015066142A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/062843
申请日：2014-10-29
发明人： RAJAEE, Omid , ALLADI, Dinesh J.
CPC分类号： H03K3/0375 , H03K3/356034 , H03K3/356069
摘要： The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters (204, 205 and 206, 207) are configured back to back to latch a signal. Each inverter includes a capacitor (C1, C2) configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages (Vip, Vin) are received on control terminals of differential transistors (201, 202), and a differential output signal (Out1, Out2) is coupled to two back to back inverters. In one embodiment, a circuit is disabled (latch signal at 0) and a voltage on a control terminal of a transistor (204, 206) in an inverter is set below a reference (Vref), such as a power supply (Vs), to increase the speed of the circuit.
摘要翻译： 本公开包括用于锁存信号的电路和方法。 在一个实施例中，两个反相器（204,205和206,207）被背靠背配置以锁存信号。 每个逆变器包括配置在逆变器晶体管的控制端之间的电容器（C1，C2）。 在一个实施例中，电路是比较器的一部分。 第一和第二电压（Vip，Vin）被接收在差分晶体管（201,202）的控制端上，并且差分输出信号（Out1，Out2）耦合到两个背靠背的反相器。 在一个实施例中，电路被禁用（锁存信号为0），并且反相器中的晶体管（204,206）的控制端子上的电压被设置在诸如电源（Vs）的参考电压（Vref）之下， 以提高电路的速度。
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