公开(公告)号：WO2023033958A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/038712

申请日：2022-07-28

Applicant: APPLE INC.

Inventor： HUBERTY, Tyler J. ,  VENKATRAMAN, Vivek ,  GUPTA, Sandeep ,  FURBISH, Eric J. ,  SRIDHARAN, Srinivasa Rangan ,  MEIER, Stephan G.

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0888 ,  G06F12/0844

Abstract: A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

公开(公告)号：WO2023033955A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/038644

申请日：2022-07-28

Applicant: APPLE INC.

Inventor： NATARAJAN, Rohit ,  SCHULZ, Jurgen M. ,  SHULER, Christopher D. ,  GUPTA, Rohit K. ,  ZOU, Thomas T. ,  SRIDHARAN, Srinivasa Rangan

IPC: G06F12/0802 ,  G06F3/06

Abstract: An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.

公开(公告)号：WO2022216597A1

公开(公告)日：2022-10-13

申请号：PCT/US2022/023296

申请日：2022-04-04

Applicant: APPLE INC.

Inventor： GARG, Gaurav ,  LAHAV, Sagi ,  LEVY-RUBIN, Lital ,  WILLIAMS, III, Gerard ,  NASSAR, Samer ,  HAMMARLUND, Per H. ,  KAUSHIKKAR, Harshavardhan ,  SRIDHARAN, Srinivasa Rangan ,  GONION, Jeff ,  VASH, James

IPC: G06F12/0831

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.