公开(公告)号：WO2021096530A1

公开(公告)日：2021-05-20

申请号：PCT/US2019/061731

申请日：2019-11-15

Applicant: APPLIED MATERIALS, INC.

Inventor： KANG, Chung-Shin ,  DONG, Yinfeng ,  HUNG, Rick R. ,  YANG, Yao Cheng ,  KAO, Tsaichuan

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/66 ,  H01L21/67

Abstract: A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.

公开(公告)号：WO2021061092A1

公开(公告)日：2021-04-01

申请号：PCT/US2019/052449

申请日：2019-09-23

Applicant: APPLIED MATERIALS, INC.

Inventor： KANG, Chung-Shin ,  LAIDIG, Thomas ,  DONG, Yinfeng ,  YANG, Yao-Cheng ,  HUNG, Chen-Chien ,  KAMALAPURA, Shivaraj Gururaj ,  KAO, Tsaichuan

IPC: G03F7/20 ,  H01L21/027

Abstract: A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.

公开(公告)号：WO2023014443A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/034170

申请日：2022-06-20

Applicant: APPLIED MATERIALS, INC.

Inventor： COSKUN, Tamer ,  KEMELDINOV, Aidyn ,  KANG, Chung-Shin ,  HOLLERBACH, Uwe ,  LAIDIG, Thomas L.

IPC: G03F7/20

Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

公开(公告)号：WO2021076120A1

公开(公告)日：2021-04-22

申请号：PCT/US2019/056512

申请日：2019-10-16

Applicant: APPLIED MATERIALS, INC.

Inventor： KANG, Chung-Shin ,  JI, Hongbin ,  COSKUN, Tamer ,  CHEN, Jang Fung ,  CHUNDER, Anindarupa ,  VAN DEN BROEKE, Douglas

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/66 ,  H01L21/67

Abstract: Embodiments disclosed herein relate to lithography systems and methods of making patterns. The lithography system includes various components for creating masks, patterning substrates, performing metrology on the patterned substrates, and comparing metrology values to the mask. The method of forming patterns includes comparing the patterned substrate to the mask, and determining a new mask that incorporates the corrections in patterning from the previous mask. The method can be repeated several times, in order to sequentially improve the quality of the mask used for lithography in the lithography system. The integrated lithography system reduces time of use and cost for the user.