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    A DATA PROCESSING APPARATUS AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY
    1.
    发明申请
    A DATA PROCESSING APPARATUS AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY 审中-公开
    一种用于移动寄存器和存储器之间的数据的数据处理装置和方法

    公开(公告)号：WO2005057405A1

    公开(公告)日：2005-06-23

    申请号：PCT/GB2004/002830

    申请日：2004-07-01

    Applicant: ARM LIMITED

    Inventor： FORD, Simon, Andrew ,  SYMES, Dominic, Hugo ,  ROSE, Andrew, Christopher ,  LUTZ, David, Raymond ,  HINDS, Christopher, Neal

    IPC: G06F9/312

    CPC classification number: G06F9/3887 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/3822 ,  G06F9/3885

    Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements occupying different lanes of parallel processing in at least one of the registers. Access logic is provided which is responsive to a single access instruction to move a plurality of data elements between a chosen one of the lanes in specified registers and a structure within memory having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is operation to arrange the plurality of data elements as they are moved such that data elements of different components are stored in different specified registers within the chosen lane whilst in memory the data elements are stored as the structure.

    Abstract translation: 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以并行地执行对至少一个寄存器中的并行处理的不同通道的多个数据元素的数据处理操作。 提供访问逻辑，其响应于单个访问指令，以在指定的寄存器中的所选择的一个通道中移动多个数据元素，并且具有结构格式的结构格式，所述结构格式具有多个组件。 单个访问指令标识结构格式中的组件的数量，并且访问逻辑是在移动多个数据元素时排列多个数据元素的操作，使得不同组件的数据元素存储在所选择的通道内的不同指定的寄存器中，同时 存储数据元素作为结构存储。

    OVERFLOW OR UNDERFLOW HANDLING FOR ANCHORED-DATA VALUE
    4.
    发明申请
    OVERFLOW OR UNDERFLOW HANDLING FOR ANCHORED-DATA VALUE 审中-公开

    公开(公告)号：WO2020161457A1

    公开(公告)日：2020-08-13

    申请号：PCT/GB2019/053363

    申请日：2019-11-28

    Applicant: ARM LIMITED

    Inventor： LUTZ, David, Raymond ,  BURGESS, Neil ,  HINDS, Christopher, Neal

    IPC: G06F9/30 ,  G06F9/38

    Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

    A DATA PROCESSING APPARATUS AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY
    6.
    发明申请
    A DATA PROCESSING APPARATUS AND METHOD FOR MOVING DATA BETWEEN REGISTERS AND MEMORY 审中-公开
    用于移动寄存器和存储器之间的数据的数据处理装置和方法

    公开(公告)号：WO2005057406A1

    公开(公告)日：2005-06-23

    申请号：PCT/GB2004/002847

    申请日：2004-07-01

    Applicant: ARM LIMITED

    Inventor： FORD, Simon, Andrew ,  SYMES, Dominic, Hugo ,  ROSE, Andrew, Christopher ,  LUTZ, David, Raymond ,  HINDS, Christopher, Neal

    IPC: G06F9/312

    CPC classification number: G06F9/30167 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145

    Abstract: A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.

    Abstract translation: 提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。 数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。 处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。 访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个 组件。 单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是 存储为结构数组。

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