公开(公告)号：WO0118953A3

公开(公告)日：2001-12-13

申请号：PCT/US0040852

申请日：2000-09-08

Applicant: ATHEROS COMM INC

Inventor： SU DAVID K ,  ZARGARI MASOUD

IPC: H03D7/14

CPC classification number: H03D7/1441 ,  H03D7/1408 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0043

Abstract: A mixing apparatus includes a Gilbert cell connected to a first load and a second load. In one embodiment each load contains transistors that are configured as a diode and a triode, where these circuits are additively combined to achieve substantially linear voltage-current characteristics over a predetermined range. The mixing apparatus takes two pairs of differential inputs and produces a pair of differential outputs. Because of the substantial linearity of the loads, the inputs and outputs of the mixing apparatus are acceptable over a relatively large range of input settings. In other embodiments each load may contain a transistor configured as a triode and a resistor, where these circuits are likewise additively combined to achieve substantially linear voltage-current characteristics over a predetermined range.

Abstract translation: 混合装置包括连接到第一负载和第二负载的吉尔伯特电池。 在一个实施例中，每个负载包含被配置为二极管和三极管的晶体管，其中这些电路被加法组合以在预定范围内实现基本上线性的电压 - 电流特性。 混合装置采用两对差分输入，并产生一对差分输出。 由于负载的实质线性，混合装置的输入和输出在相对大的输入设置范围内是可以接受的。 在其他实施例中，每个负载可以包含配置为三极管和电阻器的晶体管，其中这些电路同样地被加法组合以在预定范围内实现基本上线性的电压 - 电流特性。

公开(公告)号：WO03094344B1

公开(公告)日：2004-05-27

申请号：PCT/US0313493

申请日：2003-04-29

Applicant: ATHEROS COMM INC

Inventor： JEN HUNG-MIN ,  SU DAVID K

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/28

CPC classification number: H03F3/45475 ,  H03F1/3211 ,  H03F3/211 ,  H03F3/45183 ,  H03F3/45632 ,  H03F3/72 ,  H03F2203/21175 ,  H03F2203/45138 ,  H03F2203/45318 ,  H03F2203/45332 ,  H03F2203/45458 ,  H03F2203/45464 ,  H03F2203/45512 ,  H03F2203/45702 ,  H03F2203/45704 ,  H03F2203/7221 ,  H03F2203/7236 ,  H03G1/0029

Abstract: The present invention provides a variable gain amplifier with a plurality of gain stages in which each of the gain stages is implemented using a circuit that implements a neutralization approach. This variable gain amplifier provides stable operation characteristics as different gain stages within the variable gain amplifier are turned on and off. This variable gain amplifier also increases linearity across the entire operating range. Additionally, the variable gain amplifier of the present invention provides a constant input impedance through different gain settings. Further, the present invention provides a variable gain amplifier in which each of the various gain stages therein maximize the available voltage swing. Finally, this variable gain amplifier improves common-mode rejection performance and attenuates unwanted harmonics.

Abstract translation: 本发明提供一种具有多个增益级的可变增益放大器，其中使用实现中和方式的电路来实现每个增益级。 该可变增益放大器提供稳定的操作特性，因为可变增益放大器内的不同增益级被打开和关闭。 该可变增益放大器还可以在整个工作范围内提高线性度。 此外，本发明的可变增益放大器通过不同的增益设置提供恒定的输入阻抗。 此外，本发明提供了一种可变增益放大器，其中各种增益级中的每个增益级中的可用电压摆幅​​最大化。 最后，该可变增益放大器提高了共模抑制性能，并衰减了不需要的谐波。

公开(公告)号：WO02052728A3

公开(公告)日：2003-11-20

申请号：PCT/US0148874

申请日：2001-12-17

Applicant: ATHEROS COMM INC

Inventor： SU DAVID K ,  YUE CHIK PATRICK ,  WEBER DAVID J ,  ZARGARI MASOUND

IPC: H03K23/66 ,  H03L7/089 ,  H03L7/095 ,  H03L7/099 ,  H03L7/10 ,  H03L7/183 ,  H03L7/193

CPC classification number: H03L7/099 ,  H03K23/667 ,  H03L7/089 ,  H03L7/095 ,  H03L7/10 ,  H03L7/193 ,  Y10S331/02

Abstract: The present invention provides a synthesizer having an efficient lock detect signal generator, an extended range VCO that can operate within any one of a plurality of adjacent characteristic curves defined by a plurality of adjacent regions, and a divide circuit implemented using only a single counter along with a decoder. This allows for a method of operating the synthesizer, methods of establishing or reestablishing a lock condition using the extended range VCO, and a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.

Abstract translation: 本发明提供一种合成器，其具有有效的锁定检测信号发生器，能够在由多个相邻区域限定的多个相邻特性曲线中的任何一个中操作的扩展范围VCO，以及仅使用单个计数器实现的除法电路 与解码器。 这允许操作合成器的方法，使用扩展范围VCO建立或重新建立锁定条件的方法，以及设计多个除法电路的方法，每个除法电路使用相同的单个计数器并且每个使用不同的解码器。