公开(公告)号：WO2023077019A1

公开(公告)日：2023-05-04

申请号：PCT/US2022/078807

申请日：2022-10-27

Applicant: ATIEVA, INC.

Inventor： JAYARAMAREDDY, Tejeswini ,  SRIRAMANENI, Ramesh ,  TRIVEDI, Amiya ,  DEVNALE, Vishal Dayanand

IPC: G06F9/445 ,  H04L9/08 ,  H04L9/32

Abstract: Described techniques provide addressing schemes that account for address differences between active and inactive memory banks in dual bank memory architectures used in software over the air (SOTA) updates implemented using address swapping between the dual memory banks, including providing address translations where needed to obtain one standard addressing scheme for purposes of SOTA updates. A timing and implementation of authentication and booting techniques may ensure that signature authentication and boot processes use correct memory addresses across the dual memory banks to enable updates of both an application and a bootloader to occur. Swapping techniques are described that enable robust, secure swapping between the banks, and that enable SOTA updates to hardware security manager (HSM) software, while ensuring use of such HSM software in dual bank scenarios.