公开(公告)号：WO2014106844A1

公开(公告)日：2014-07-10

申请号：PCT/IL2014/050005

申请日：2014-01-02

Applicant: B.G. NEGEV TECHNOLOGIES AND APPLICATIONS LTD.

Inventor： GREENBERG, Shlomo ,  PAPERNO, Evgeny ,  RABINOWICZ, Yossi ,  TSECHANSKI, Ron ,  MANOR, Erez ,  WEBER, Ori

IPC: H01L21/02 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/504 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/78

Abstract: The invention relates to a method for reducing the number of flip-flops in a VLSI design that require data retention, thereby eliminating the respective backup cells for those flip flops, the method comprises the steps of: (a) defining one or more criteria for non-essentiality of backup cells! (b) during the physical design stage, analyzing the VLSI design based on said one or more criteria for non- essentiality, and finding those flip-flops that meet these criteria, wherein said analysis is performed at the gate level, independent from any higher level representation of the design; and (c) eliminating from the VLSI design those backup cells for all non-essential flip-flops that meet one or more of said criteria for non-essentiality, thereby leaving in the design only those backup cells for those flip-flops that do not meet any of said criteria.

Abstract translation: 本发明涉及一种用于减少VLSI设计中需要数据保持的触发器数量的方法，从而消除了那些触发器的相应备用单元，该方法包括以下步骤：（a）定义一个或多个标准 备份单元非必要性！ （b）在物理设计阶段，基于所述一个或多个非必要性标准来分析VLSI设计，并且找到满足这些标准的那些触发器，其中所述分析在门级执行，独立于任何更高的 设计的层次表示; 并且（c）从满足一些或多个所述非本质标准的所有非本质触发器的VLSI设计中消除这些备用单元，从而在设计中仅留下那些不起作用的那些触发器的备用单元 符合任何上述标准。