Abstract:
A radar warning receiver is implemented in low cost integrated circuit form utilizing only one analog component, namely a limiting amplifier. By taking the output of the limiting amplifier and utilizing monobit sampling of the output it has been found that one can provide an integrated circuit single chip radar warning receiver using delay correlation to extract frequency, amplitude and modulation type from signals at or below the noise level.
Abstract:
What is provided is a receiver-on-a-chip comprising a monolithic integrated circuit that reduces the receiver to a cigarette-pack-sized assembly mountable directly at an antenna element, with a much-increased operational bandwidth and instantaneous bandwidth, increased dynamic range and with a two-order-of-magnitude decrease in size and weight. Moreover, because of the elimination of all of the I/O drivers and attendant circuitry, power consumption is reduced by two-thirds, whereas the mean time before failure is increased to 10,000 hours due to the robustness of the monolithic integrated circuit and use of fiber optics.
Abstract:
A radar warning receiver is disclosed. The radar warning receiver includes an antenna, a signal detection unit, a signal identification unit and an alarm. The antenna collects radio frequency (RF) signals. The signal detection unit is configured to generate a group of frequency and amplitude signals based on the collected RF signals. Specifically, the signal detection unit includes a pair of limiting amplifiers for converting the collected RF signals into corresponding pulsed output signals that track the actual frequency oscillations of the collected RF signals, and a pseudo-random noise generator for injecting noise into one of the limiting amplifiers. Based on the frequency and amplitude signals, the signal identification unit determines whether or not any of the collected RF signals includes a threat signal. The alarm is utilized to present a threat signal to a human operator.
Abstract:
The present invention relates to a device and method that digitally replicates the analog processing that is normally associated with an instantaneous frequency measurement device. Specifically, the present relates to a digital frequency measurement device comprising: a filter, where the filter receives an input RF signal and transmits an output signal centered around a desired frequency; a limiting amplifier downstream of the filter, where the amplifier receives and amplifies the output signal; a deserializer downstream of the amplifier that continuously samples the output signal from the limiting amplifier; and a digital frequency measurement processor (DFM), where the DIM receives data at a rate of 1/16 of the deserializer sample rate. The DIM transforms the data into multiples stages that are combined in order to produce an estimate of the input signal, where the DIM is implemented through a digital processing device.