公开(公告)号：WO1995026529A1

公开(公告)日：1995-10-05

申请号：PCT/US1995003006

申请日：1995-03-14

Applicant: BULL HN INFORMATION SYSTEMS INC.

Inventor： BULL HN INFORMATION SYSTEMS INC. ,  SHELLY, William, A. ,  LANGE, Ronald, E. ,  BOOTHROYD, Donald, C.

IPC: G06F11/00

CPC classification number: G06F11/1654 ,  G06F11/10 ,  G06F11/1633

Abstract: In order to validate data manipulation results in a CPU which incorporates duplicate basic processing units (60, 61) for integrity, which BPUs (60, 61) are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation to obtain first and second data manipulation results, which should be identical, and a cache unit (70) for receiving data manipulation results from both BPUs (60, 61) and for transferring specified information words simultaneously to both BPUs (60, 61) upon request. In each BPU (60, 61), parity is generated for control groups, which are made up of cache interface control signals generated by each BPU (60, 61). Parity for the groups sent to the cache unit (70) and the other respective BPU (60, 61) are checked for errors in both the cache unit (70) and the respective BPU (60, 61), and in the event that an error is sensed, an error signal is issued to institute appropriate remedial action.

Abstract translation: 为了验证在完整性中包含重复的基本处理单元（60,61）的CPU中的数据操纵结果，哪些BPU（60,61）通常在单个VLSI电路芯片上实现，并且能够执行单个和 双精度数据操作以获得应该相同的第一和第二数据操作结果，以及用于从两个BPU（60,61）接收数据操作结果并且将指定信息字同时传送到两个BPU（60）的高速缓存单元（70） ，61）。 在每个BPU（60,61）中，对于由每个BPU产生的高速缓存接口控制信号（60,61）组成的控制组产生奇偶校验。 检查发送到高速缓存单元（70）和另一个相应BPU（60,61）的组的奇偶校验在高速缓存单元（70）和相应BPU（60,61）两者中的错误，并且如果 检测到错误，发出错误信号以进行适当的补救措施。