CONTROL LOGIC PERFORMANCE OPTIMIZATIONS FOR UNIVERSAL SERIAL BUS POWER DELIVERY CONTROLLER

    公开(公告)号:WO2022051410A1

    公开(公告)日:2022-03-10

    申请号:PCT/US2021/048732

    申请日:2021-09-01

    Abstract: An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.

    SWITCHING CLOCK PHASE SHIFT FOR MULTI-PORT BUCK-BOOST CONVERTER

    公开(公告)号:WO2022051180A1

    公开(公告)日:2022-03-10

    申请号:PCT/US2021/047910

    申请日:2021-08-27

    Abstract: A multi-port USB Power Delivery Type-C (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.

    PRIMARY CONTROLLER CALIBRATION AND TRIMMING USING SECONDARY CONTROLLER IN SECONDARY-CONTROLLED FLYBACK CONVERTERS

    公开(公告)号:WO2020263470A1

    公开(公告)日:2020-12-30

    申请号:PCT/US2020/034027

    申请日:2020-05-21

    Inventor: RAI, Hariom

    Abstract: Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.

    COMMUNICATING FAULT INDICATIONS BETWEEN PRIMARY AND SECONDARY CONTROLLERS IN A SECONDARY-CONTROLLED FLYBACK CONVERTERS

    公开(公告)号:WO2020263530A1

    公开(公告)日:2020-12-30

    申请号:PCT/US2020/036201

    申请日:2020-06-04

    Abstract: Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.

    LIGHT EMITTING DRIVER CIRCUIT WITH COMPENSATION AND METHOD
    7.
    发明申请
    LIGHT EMITTING DRIVER CIRCUIT WITH COMPENSATION AND METHOD 审中-公开
    具有补偿和方法的发光驱动电路

    公开(公告)号:WO2010037015A1

    公开(公告)日:2010-04-01

    申请号:PCT/US2009/058588

    申请日:2009-09-28

    CPC classification number: H05B33/0818

    Abstract: A light emitting driver circuit, system, and method are provided. The driver circuit system and method can be implemented in various ways. An embodiment includes a bypass circuit which diverts current from the LEDs whenever a switch coupled to the LEDs incurs residual current when turned off. In an additional or alternative embodiment, the residual current can be sensed and the amount of residual current used to trigger fetching of a compensation value. That compensation value can change a dimming function forwarded to the switch in order to compensate for, offset, or substantially eliminate the residual current through that switch.

    Abstract translation: 提供了一种发光驱动电路,系统和方法。 驱动电路系统和方法可以以各种方式实现。 一个实施例包括旁路电路,每当耦合到LED的开关在关断时产生剩余电流时,该旁路电路从LED转向电流。 在附加或替代实施例中,可以感测剩余电流以及用于触发获取补偿值的剩余电流量。 该补偿值可以改变转发到开关的调光功能,以补偿,偏移或基本消除通过该开关的剩余电流。

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