公开(公告)号：WO2018098087A1

公开(公告)日：2018-05-31

申请号：PCT/US2017/062632

申请日：2017-11-20

Applicant: DEGIRUM CORPORATION

Inventor： TAM, Kit S. ,  LEE, Winston

IPC: G06F15/16 ,  H04B10/20 ,  H04B10/275 ,  H04L5/14

Abstract: A permutated ring network includes a plurality of bi-directional source-synchronous ring networks, each having a plurality of data transport stations, and a plurality of communication nodes. Each of the communication nodes is coupled to one of the data transport stations in each of the plurality of bi-directional source-synchronous ring networks.

公开(公告)号：WO2019212664A1

公开(公告)日：2019-11-07

申请号：PCT/US2019/024799

申请日：2019-03-29

Applicant: DEGIRUM CORPORATION

Inventor： LEE, Winston

IPC: H04J3/06 ,  G06F1/08 ,  G06F1/10 ,  G06F5/06 ,  G06F5/08 ,  H04L12/42

Abstract: A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.

公开(公告)号：WO2019199490A1

公开(公告)日：2019-10-17

申请号：PCT/US2019/024793

申请日：2019-03-29

Applicant: DEGIRUM CORPORATION

Inventor： LEE, Winston ,  TAM, Kit S.

IPC: G06F5/06 ,  G11C8/00

Abstract: A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (SMIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. SMIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.