公开(公告)号：WO2018098084A3

公开(公告)日：2018-05-31

申请号：PCT/US2017/062627

申请日：2017-11-20

Applicant: DEGIRUM CORPORATION

Inventor： TAM, Kit S.

IPC: H04J3/02 ,  H04L12/02 ,  H04L12/20

Abstract: A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking scheme, such that there is no need to build an extensive low skew clock-tree across a large die area. A single reference clock signal is generated within a root node, and is routed through each of the nodes of the ring network in a unidirectional manner. Each node includes a timestamp counter and a color bit register, which store values that enable the node to resolve ordered transaction messages issued by the other nodes in a precise order, even though the nodes are operating independently, and receive the various transaction messages in totally different timing orders. Because the control logic is distributed among the nodes, no centralized controller is necessary.

公开(公告)号：WO2018098087A1

公开(公告)日：2018-05-31

申请号：PCT/US2017/062632

申请日：2017-11-20

Applicant: DEGIRUM CORPORATION

Inventor： TAM, Kit S. ,  LEE, Winston

IPC: G06F15/16 ,  H04B10/20 ,  H04B10/275 ,  H04L5/14

Abstract: A permutated ring network includes a plurality of bi-directional source-synchronous ring networks, each having a plurality of data transport stations, and a plurality of communication nodes. Each of the communication nodes is coupled to one of the data transport stations in each of the plurality of bi-directional source-synchronous ring networks.

公开(公告)号：WO2020185634A1

公开(公告)日：2020-09-17

申请号：PCT/US2020/021601

申请日：2020-03-07

Applicant: DEGIRUM CORPORATION

Inventor： TAM, Kit S.

IPC: G06F15/173 ,  G06F15/167

Abstract: A computer architecture that connects a plurality of compute engines and memory banks using one or more permutated ring networks to provide a scalable, high-bandwidth, low-latency point-to-point multi-chip communications solution.

公开(公告)号：WO2019199490A1

公开(公告)日：2019-10-17

申请号：PCT/US2019/024793

申请日：2019-03-29

Applicant: DEGIRUM CORPORATION

Inventor： LEE, Winston ,  TAM, Kit S.

IPC: G06F5/06 ,  G11C8/00

Abstract: A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (SMIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. SMIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.

公开(公告)号：WO2018098084A2

公开(公告)日：2018-05-31

申请号：PCT/US2017/062627

申请日：2017-11-20

Applicant: DEGIRUM CORPORATION

Inventor： TAM, Kit S.

IPC: H04L12/42 ,  H04L7/04

Abstract: A ring network architecture includes multiple communication nodes configured in a ring. Wave pipelining is used to provide for high bandwidth and low latency on-chip communications. Each node implements a source-synchronized clocking scheme, such that there is no need to build an extensive low skew clock-tree across a large die area. A single reference clock signal is generated within a root node, and is routed through each of the nodes of the ring network in a unidirectional manner. Each node includes a timestamp counter and a color bit register, which store values that enable the node to resolve ordered transaction messages issued by the other nodes in a precise order, even though the nodes are operating independently, and receive the various transaction messages in totally different timing orders. Because the control logic is distributed among the nodes, no centralized controller is necessary.