公开(公告)号：WO2021092601A2

公开(公告)日：2021-05-14

申请号：PCT/US2020/067195

申请日：2020-12-28

Applicant: FUTUREWEI TECHNOLOGIES, INC.

Inventor： MCHUGH, Timothy ,  IEHL, Brian ,  CONNELL, Larry

IPC: H03K5/133 ,  H03K5/156 ,  H03K5/1565

Abstract: A frequency doubler circuit is presented that provides a way to quickly and simply calibrate the phase delay required for a differential 50% output duty cycle frequency doubler in a manner that is low in cost and current drain. A fully differential approach is used, in which the components of a differential input signal (clkjn, clkjnb) are used to generate a differential output signal (clk_out, clk_outb) and a delayed differential output signal (clk_dly_out, clk_dly_outb). The differential output signal and the delayed differential output signal are combined in the logic circuitry (551, 553) to determine the components of the differential double frequency output signal (2x_clk, 2x_clkb). Outputs of the logic circuitry are used to adjust the amount of delay (541: control) in the delayed output signal so that the double frequency output signal has a duty cycle of 50%. In some embodiments, the positive and negative components of the delayed signal can be adjusted independently (541: control).