公开(公告)号：WO1981001782A1

公开(公告)日：1981-06-25

申请号：PCT/US1980001594

申请日：1980-12-01

Applicant: GENERAL ELECTRIC CO

Inventor： GENERAL ELECTRIC CO ,  HUGHES W ,  HACKERT W

IPC: H03L07/10

CPC classification number: H03L7/185 ,  H03L7/10 ,  H03L7/14 ,  Y10S331/02

Abstract: A phase-locked loop circuit, having an oscillator (15) controlled by a voltage (VO') related to phase difference between a reference signal (fL) and a loop signal (fL'), is stabilized by a crystal oscillator (18). The voltage controlled oscillator signal (f1) is frequency-substracted from the crystal oscillator signal frequency (fx) to provide an input signal (fS) to a frequency-arithmetic synthesizer (21) which provides the loop signal (fL') to the phase detector (12) for comparison with the coming reference signal. Use of a frequency-adder circuit between the voltage controlled oscillator (15) and the frequency-subtractor (16) and receiving an addition frequency derived from the frequency-arithmetic synthesizing circuit (21) is utilized to decrease the loop gain and provide enhanced characteristics.

公开(公告)号：WO1981001929A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001692

申请日：1980-12-22

Applicant: GENERAL ELECTRIC CO

Inventor： GENERAL ELECTRIC CO ,  HUGHES W

IPC: H04B01/10

CPC classification number: H04L27/2276

Abstract: A receiver for recovering digital data from a phase-shift-modulated carrier in a data communications system, utilizes a relatively wide band-pass filter (30) providing the received modulated signal to a pair of phase-locked loops. The first phase-locked loop (40, 44, 46) provides a local oscillator signal (at 46b) tracking the exact frequency and phase of the received signal (fin), which is itself locked to a multiple of a system-wide frequency. The second phase-locked loop (42, 52, 60, 62) acts as a synchronous data detector. Inversion circuitry (48), in the first phase-lock loop, is controlled by the detected data output from the second phase-lock loop, for preventing the 180 phase modulation from disturbing the frequency-tracking local oscillator phase-lock loop.

公开(公告)号：WO1981002498A1

公开(公告)日：1981-09-03

申请号：PCT/US1981000197

申请日：1981-02-17

Applicant: GENERAL ELECTRIC CO

Inventor： GENERAL ELECTRIC CO ,  HUGHES W

IPC: H04L27/18

CPC classification number: H04L27/18

Abstract: A transceiver for a phase-shift-modulated carrier data communications system, includes a digital-data recovering receiver (16) having relatively wide band pass filters (74) and a complimentary integrate-and-dump data detector (94). A pseudo-bandpass-filtered, modulated-carrier synthesizer (200, 202, 204, 206) provides a transmission signal, under control of a frequency-arithmetic multiple-frequency synthesizer (20) which is also utilized to provide all required frequencies to the receiver mixers (75, 76) and baud synchronization circuitry (96). All transceiver frequencies are locked to the instantaneous frequency of a system-wide signal.

公开(公告)号：WO1981001934A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001693

申请日：1980-12-22

Applicant: GENERAL ELECTRIC CO

Inventor： GENERAL ELECTRIC CO ,  HUGHES W

IPC: H04L27/20

CPC classification number: H04L27/2092

Abstract: The modulated carrier in a frequency-multiplexed digital communications system is synthesized with each baud of the modulated carrier derived from data stored in a read-only memory (32). The carrier envelope shape is selected to reduce the sidebands of the digitally modulated carrier and thus reduce interchannel interference. The read-only memory digital output (32b) is applied to a digital-to-analog converter (34) for synthesis of an analog voltage, representing the modulated sinusoidal carrier, having reduced higher frequency content, without the necessity for use of a costly, narrow-bandpass filter.

公开(公告)号：WO1981001928A1

公开(公告)日：1981-07-09

申请号：PCT/US1980001694

申请日：1980-12-22

Applicant: GENERAL ELECTRIC CO

Inventor： GENERAL ELECTRIC CO ,  HUGHES W

IPC: H03L07/00

CPC classification number: H04L7/0331 ,  H03L7/0992

Abstract: Apparatus for synchronizing the bit clock in a digital receiver to be in phase with bits of a received data stream, utilizes a frequency source locked to a system-wide frequency (fm) and frequency-arithmetic means (18, 14, 16) for providing first and second local frequencies respectively slightly greater and slightly less than a sub-multiple of the system-wide frequency. Countdown circuitry (11) provides a multiplicity of local clock phases at the local clock frequency for phase comparison with the clock frequency derived from the received data stream and for subsequent digital phase adjustment to cause the local baud clock to track the received data stream bit transition frequency.