公开(公告)号：WO2022208378A1

公开(公告)日：2022-10-06

申请号：PCT/IB2022/052931

申请日：2022-03-30

Applicant: GSI TECHNOLOGY INC.

Inventor： ILAN, Dan ,  SERY, Tomer

IPC: G11C13/00 ,  G06F40/284 ,  G06F40/289 ,  G11C7/12

Abstract: A system for N-gram classification in a field of interest via hyperdimensional computing includes an associative memory array and a controller. The associative memory array stores hyperdimensional vectors in rows of the array. The hyperdimensional vectors represent symbols in the field of interest and the array includes bit-line processors along portions of bit-lines of the array. The controller activates rows of the array to perform XNOR, permute, and add operations on the hyperdimensional vectors with the bit-line processors, to encode N-grams, having N symbols therein, to generate fingerprints of a portion of the field of interest from the N-grams, to store the fingerprints within the associative memory array, and to match an input sequence to one of the stored fingerprints.

公开(公告)号：WO2022201005A1

公开(公告)日：2022-09-29

申请号：PCT/IB2022/052572

申请日：2022-03-21

Applicant: GSI TECHNOLOGY INC.

Inventor： SHU, LeeLean ,  ILAN, Dan ,  SERY, Tomer ,  AKERIB, Avidan

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4072

Abstract: A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null read result.

公开(公告)号：WO2022167945A1

公开(公告)日：2022-08-11

申请号：PCT/IB2022/050895

申请日：2022-02-02

Applicant: GSI TECHNOLOGY INC.

Inventor： ILAN, Dan

IPC: H04L9/00 ,  G06F7/58 ,  H02H3/05

Abstract: A system for parallel combinatorial design includes a processor, an in-memory vector processor and a storage unit. The processor includes a seed generator, a Cspan generator and a rule checker. The seed generator generates at least one seed to generate combinations of length N, defining a space of N choices of which M choices are to be selected. The Cspan generator generates at least one combination from the at least one seed and stores each combination in a separate column of the in-memory vector processor. The rule checker performs a parallel search at least in the in-memory vector processor for combinations which satisfy a rule and the storage unit receives search results of the rule checker from the in-memory vector processor.