公开(公告)号：WO2017031974A1

公开(公告)日：2017-03-02

申请号：PCT/CN2016/075997

申请日：2016-03-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： LEE, Chang ,  HAMELIN, Louis-Philippe ,  SINN, Peter Man Kin

IPC: G06F9/38

CPC classification number: G06F9/30079 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/3016 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3871

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated to each one of said at least one resource of interest. The method can include : decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract translation: 处理器芯片可以具有共享包括感兴趣的至少一个资源的多个资源的预执行流程，资源跟踪器具有与所述至少一个所述资源中的每个资源相关联的多于一个信用单元。 所述方法可以包括：对所述指令数据进行解码以确定资源需求，其包括从所述信用单元为所述至少一个感兴趣的资源所需的虚拟信用量，检查所述资源跟踪器以获得所述数量的虚拟信用，以及如果 建立所述虚拟信用量的可用性，i）分派指令数据，以及ii）从资源跟踪器中减去所述信用的数量。

公开(公告)号：WO2017031976A1

公开(公告)日：2017-03-02

申请号：PCT/CN2016/075999

申请日：2016-03-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： HAMELIN, Louis-Philippe ,  SINN, Peter Man Kin ,  LEE, Chang ,  ALEPIN, Paul ,  KAMENDJE TCHOKOBOU, Guy-Armand ,  DARCY, Olivier ,  VINCENT, John Edward.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/38 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3867 ,  G06F9/3871

Abstract: A method can be performed in a processor integrated circuit having an instruction decoder (18, 118) and a plurality of shared resources (14, 114), a resource tracker (16, 116) having a plurality of credit units (22) associated to corresponding ones of the shared resources (14, 114) in a manner to be updatable based on availability of the shared resources (14, 114), a resource matcher (28, 128) connected to receive a resource requirement signal from the decoder (18, 118) and connected to receive a resource availability signal from the resource tracker (16, 116). The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units (22), and preventing the resource matcher (28, 128) from performing a subsequent determination for given period of time after the positive determination.

Abstract translation: 一种方法可以在具有指令解码器（18,118）和多个共享资源（14,114）的处理器集成电路中执行，资源跟踪器（16,116）具有多个信用单元（22） 基于共享资源（14,114）的可用性，可以以可更新的方式对应的共享资源（14,114）;资源匹配器（28,128），连接到从解码器（18,114）接收资源需求信号 ，118）并连接以从资源跟踪器（16,116）接收资源可用性信号。 该方法可以包括：确定资源需求信号是否与资源可用性信号相匹配，并且在肯定确定时，发送对应的指令数据，更新对应的一个或多个信用单元（22）的状态 ），并且防止资源匹配器（28,128）在肯定确定之后的给定时间段内执行随后的确定。

公开(公告)号：WO2017031975A1

公开(公告)日：2017-03-02

申请号：PCT/CN2016/075998

申请日：2016-03-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： SINN, Peter Man Kin ,  LEE, Chang ,  HAMELIN, Louis-Philippe

IPC: G06F9/26

CPC classification number: G06F9/30061 ,  G06F9/30058 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3851 ,  G06F9/3861

Abstract: A system and method for multi-branch switching are provided. A memory has stored therein a program comprising at least one sequence of instructions, the at least one sequence of instructions comprising a plurality of branch instructions, at least one branch of the program reached upon execution of each one of the plurality of branch instructions. The processor is configured for fetching the plurality of branch instructions from the memory, separately buffering each branch of the program associated with each one of the fetched branch instructions, evaluating the fetched branch instructions in parallel, and executing the evaluated branch instructions in parallel.

Abstract translation: 提供了一种多分支切换的系统和方法。 存储器中存储有包括至少一个指令序列的程序，所述至少一个指令序列包括多个分支指令，在执行多个分支指令中的每个分支指令时达到的程序的至少一个分支。 处理器被配置为从存储器取出多个分支指令，分别缓存与取出的分支指令中的每一个相关联的程序的每个分支，并行评估所获取的分支指令，并且并行执行评估的分支指令。