DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY
    1.
    发明申请
    DEVICE AND PROCESSING ARCHITECTURE FOR INSTRUCTION MEMORY EFFICIENCY 审中-公开
    设备和处理架构的指令记忆效率

    公开(公告)号:WO2017032022A1

    公开(公告)日:2017-03-02

    申请号:PCT/CN2016/080512

    申请日:2016-04-28

    Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

    Abstract translation: 描述不同的处理器架构来评估和跟踪指令所需的依赖性。 处理器可以保存或排队需要输出其他指令的指令,直到需要的数据和资源可用,这可以消除指令存储器中NOP的要求以解决依赖性和流水线危险。 处理器可以将指令数据划分为并行执行的捆绑包,并提供推测执行。 处理器可以包括实现评估单元,执行单元和终止单元的各种组件。

    PROCESSOR AND METHOD OF HANDLING AN INSTRUCTION DATA THEREIN
    2.
    发明申请
    PROCESSOR AND METHOD OF HANDLING AN INSTRUCTION DATA THEREIN 审中-公开
    处理器和处理指令数据的方法

    公开(公告)号:WO2017031976A1

    公开(公告)日:2017-03-02

    申请号:PCT/CN2016/075999

    申请日:2016-03-09

    Abstract: A method can be performed in a processor integrated circuit having an instruction decoder (18, 118) and a plurality of shared resources (14, 114), a resource tracker (16, 116) having a plurality of credit units (22) associated to corresponding ones of the shared resources (14, 114) in a manner to be updatable based on availability of the shared resources (14, 114), a resource matcher (28, 128) connected to receive a resource requirement signal from the decoder (18, 118) and connected to receive a resource availability signal from the resource tracker (16, 116). The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units (22), and preventing the resource matcher (28, 128) from performing a subsequent determination for given period of time after the positive determination.

    Abstract translation: 一种方法可以在具有指令解码器(18,118)和多个共享资源(14,114)的处理器集成电路中执行,资源跟踪器(16,116)具有多个信用单元(22) 基于共享资源(14,114)的可用性,可以以可更新的方式对应的共享资源(14,114);资源匹配器(28,128),连接到从解码器(18,114)接收资源需求信号 ,118)并连接以从资源跟踪器(16,116)接收资源可用性信号。 该方法可以包括:确定资源需求信号是否与资源可用性信号相匹配,并且在肯定确定时,发送对应的指令数据,更新对应的一个或多个信用单元(22)的状态 ),并且防止资源匹配器(28,128)在肯定确定之后的给定时间段内执行随后的确定。

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