公开(公告)号：WO2018113668A1

公开(公告)日：2018-06-28

申请号：PCT/CN2017/117201

申请日：2017-12-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  DANG, Yen ,  LEI, Gong ,  GU, Yifan ,  LEE, Hung-Yi ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  LIU, Miao

IPC: H03L7/00

Abstract: A reference-less frequency detector circuit includes a sampling circuit that is configured to generate a frequency control voltage and a switch circuit control signal based on a frequency difference between a clock signal frequency and an input data rate. The frequency control voltage has a frequency down indication and a frequency up indication. A voltage-to-current converter circuit is coupled to the sampling circuit and is configured to convert the frequency control voltage to a frequency control current based on the switch circuit control signal. The voltage-to-current converter circuit includes an output switch circuit controlled by the switch control signal and is configured to have substantially equal respective latencies for the frequency down indication and the frequency up indication.

公开(公告)号：WO2017101788A1

公开(公告)日：2017-06-22

申请号：PCT/CN2016/109930

申请日：2016-12-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  GU, Yifan ,  LEE, Hungyi ,  LEI, Gong ,  DANG, Yen ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  DUAN, Yan

IPC: H04B10/075

CPC classification number: H04B10/0775 ,  H04B10/5055 ,  H04B10/516 ,  H04B10/564 ,  H04B10/588 ,  H04L27/01

Abstract: An apparatus comprising a semiconductor chip that comprises an optical modulator configured to modulate an optical signal based on a received driver signal, a voltage-mode (VM) driver coupled to the optical modulator and configured to produce a level-shifted driver signal to modulate the optical signal, and a two-stage test interface coupled to the optical modulator and configured to receive and test the level shifted driver signal. The two-stage test interface comprises a voltage equalization stage coupled to an output-terminated buffer stage, the VM driver comprises a two-stage VM Mach-Zehnder modulator (MZM) driver that comprises a pre-driver coupled to a VM level-shifter (VMLS). The apparatus further comprises a resistor coupled to an output of the buffer stage, wherein the resistor comprises an amount of resistance that matches a termination resistance of a test equipment. The termination resistance is about 50 ohm (Ω).

Abstract translation: 一种包括半导体芯片的设备，所述半导体芯片包括：光调制器，其被配置为基于接收到的驱动信号来调制光信号;电压模式（VM）驱动器，其耦合到所述光调制器并且被配置为产生 电平移动的驱动信号以调制光信号;以及两级测试接口，耦合到光调制器并被配置为接收和测试电平移位的驱动信号。 两级测试接口包括耦合到输出端接缓冲级的电压均衡级，VM驱动器包括两级VM Mach-Zehnder调制器（MZM）驱动器，其包括耦合到VM电平移位器 （VMLS）。 该设备还包括耦合到缓冲级的输出端的电阻器，其中电阻器包括匹配测试设备的终端电阻的电阻量。 终端电阻约为50欧姆（Ω）。

公开(公告)号：WO2017167199A1

公开(公告)日：2017-10-05

申请号：PCT/CN2017/078590

申请日：2017-03-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  LEI, Gong ,  DANG, Yen ,  GU, Yifan ,  LEE, Hungyi ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  DUAN, Yan

IPC: H04J14/02

Abstract: A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

Abstract translation: 多路复用器包括：包括多路复用器输出的输出电路; 以及第一缓冲器，耦合到所述输出电路并且包括：第一选择输入端，被配置为接收第一选择信号; 第一逻辑输入，被配置为接收第一逻辑输入信号; 和第一地面; 其中所述多路复用器被配置为：当所述第一选择信号是第一值时，将所述第一逻辑输入耦合到所述多路复用器输出; 并且当第一选择信号是第二值时将第一逻辑输入耦合到第一接地。 一种方法包括：接收选择信号和第一逻辑输入信号; 当选择信号是第一值时将第一逻辑输入耦合到多路复用器输出; 并且当选择信号是第二值时将第一逻辑输入耦合到地。

公开(公告)号：WO2017071003A1

公开(公告)日：2017-05-04

申请号：PCT/CN2015/096173

申请日：2015-12-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  LEI, Gong ,  DANG, Yen ,  GU, Yifan ,  LEE, Hungyi ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  DUAN, Yan

IPC: H03L7/091

CPC classification number: H03L7/099 ,  H03D13/00 ,  H03K5/135 ,  H03K5/14 ,  H03K19/0948 ,  H03K19/20 ,  H03K2005/00078 ,  H03L7/0807 ,  H03L7/085 ,  H03L7/089 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/033

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract translation: 一种装置，包括：第一采样电路，被配置为根据数据信号对时钟信号进行采样以产生第一采样信号;第二采样电路，被配置为根据延迟信号对时钟信号进行采样， 产生第二采样信号;以及控制电路，耦合到所述第一采样电路和所述第二采样电路，其中，所述控制电路被配置为根据所述第一采样信号和所述第二采样信号执行不和和（NAND）操作以 产生激活信号以激活时钟信号的频率调整。

公开(公告)号：WO2017071002A1

公开(公告)日：2017-05-04

申请号：PCT/CN2015/096172

申请日：2015-12-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  DANG, Yen ,  LEI, Gong ,  LEE, Hungyi ,  GU, Yifan ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  DUAN, Yan

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H03F3/193 ,  H03F3/45179 ,  H03F3/45197 ,  H03F2200/451 ,  H03F2203/45488 ,  H04B10/6971 ,  H04L25/03114 ,  H04L25/03159

Abstract: An apparatus comprising an input port configured to receive an input signal propagated through a transmission link, wherein the transmission link comprises a low-frequency channel loss and a high-frequency channel loss, a continuous-time linear equalization (CTLE) circuit coupled to the input port and configured to produce an output signal according to the input signal by applying a first gain to the input signal at a first frequency to compensate the low-frequency loss, and applying a second gain to the input signal at a second frequency to compensate the high-frequency channel loss, and an output port coupled to the CTLE circuit and configured to output the output signal.

Abstract translation: 一种设备，包括：输入端口，被配置为接收通过传输链路传播的输入信号，其中所述传输链路包括低频信道损耗和高频信道损耗;连续时间线性 均衡（CTLE）电路，耦合到所述输入端口并被配置为通过以第一频率向所述输入信号施加第一增益以根据所述输入信号产生输出信号以补偿所述低频损耗，并且向所述输入端口施加第二增益 以第二频率输入信号以补偿高频信道损耗，以及耦合到CTLE电路并配置成输出输出信号的输出端口。