公开(公告)号：WO2012058757A1

公开(公告)日：2012-05-10

申请号：PCT/CA2011/001217

申请日：2011-11-01

Applicant: LINN, Yair

Inventor： LINN, Yair

IPC: H04L27/00 ,  H04B1/26 ,  H04L27/18 ,  H04L27/34 ,  H04W24/00

CPC classification number: H04L27/20 ,  H03D13/00 ,  H03J7/065 ,  H04B17/336 ,  H04B17/391 ,  H04L27/3818

Abstract: Described are a method for generating a metric that is a function of a phase difference between a modulated carrier and a local carrier, and a phase detector for performing such a method. A baseband symbol is obtained from the modulated carrier, and the phase of the symbol is determined. Assuming that the modulation used to modulate the modulated carrier has a constellation diagram with M-fold rotational symmetry, the metric can be generated from the phase by evaluating a base function that includes a triangle wave having positively and negatively sloped linear segments whose slopes have identical absolute values and that is periodic with a period of 2π/Μ radians. Alternatively or additionally, if the ideal symbol phases are uniformly distributed, the metric can be generated by evaluating a version of the base function in which the ideal symbol phases correspond to identically valued metrics located on the triangle wave.

Abstract translation: 描述了用于产生作为调制载波和本地载波之间的相位差的函数的度量的方法，以及用于执行这种方法的相位检测器。 从调制载波获得基带符号，并确定符号的相位。 假设用于调制调制载波的调制具有具有M倍旋转对称性的星座图，则可以通过评估包括具有正斜率和负斜率线性段的三角波的基函数从相位产生度量，其斜率具有相同的 绝对值，周期为2p /？ 弧度。 或者或另外，如果理想符号相位被均匀分布，则可以通过评估其中理想符号相位对应于位于三角波上的相同值的度量的基本函数的版本来生成度量。

公开(公告)号：WO2011059842A2

公开(公告)日：2011-05-19

申请号：PCT/US2010/054900

申请日：2010-10-31

Applicant: RAMBUS INC. ,  LEIBOWITZ, Brian ,  LEE, Hae-Chang ,  ARYANFAR, Farshid ,  CHANG, Kun-Yung ,  SHEN, Jie

Inventor： LEIBOWITZ, Brian ,  LEE, Hae-Chang ,  ARYANFAR, Farshid ,  CHANG, Kun-Yung ,  SHEN, Jie

CPC classification number: H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于输入信号的相位对齐而生成非零输出。 输入信号基于两个周期性信号。 当周期信号同相时，相位检测电路从另一相位检测器的输出信号中减去一个相位检测器的输出信号，以产生具有零值的信号。 或者，相位检测器产生指示周期性信号之间的相位差的相位比较信号。 响应于相位检测器的输入信号被同相对准，相位比较信号具有非零值。 输入信号基于周期性信号。 输出电路接收相位比较信号并且响应于周期性信号的相位对准而产生具有零值的输出。

公开(公告)号：WO2007127574A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/065456

申请日：2007-03-29

Applicant: MOTOROLA, INC. ,  GAILUS, Paul, H. ,  CHARASKA, Joseph, A.

Inventor： GAILUS, Paul, H. ,  CHARASKA, Joseph, A.

IPC: H03D13/00

CPC classification number: H03D13/00 ,  H03L7/0891 ,  H03L7/1976

Abstract: A phase-frequency detector (110) is provided. The phase-frequency detector can include a frequency counter delay (147) for counting cycles of an output signal to generate a divided variable frequency delayed signal (FVd 146) having a time shift. A control stage (200) coupled to the output stage generates a pump up control signal (222) and a pump down control signal (234) in response to receiving the FVd signal, a divided variable frequency signal (FV 136), and a reference frequency signal (FR 106). The time shift provides an overlap region that allows both source (350) and sink (360) currents to be provided in phase lock. In phase lock, the duration of the pump up control signal approximates the duration of the pump down control signal within a linear region of operation.

Abstract translation: 提供了一个相位频率检测器（110）。 相位频率检测器可以包括用于对输出信号的周期进行计数以产生具有时移的分频可变频率延迟信号（FVd 146）的频率计数器延迟（147）。 耦合到输出级的控制级（200）响应于接收到FVd信号，分频可变频率信号（FV 136）和参考值而产生泵浦控制信号（222）和抽空控制信号（234） 频率信号（FR 106）。 时移提供了一个重叠区域，允许在锁相中提供源极（350）和吸收（360）电流。 在锁相中，泵浦控制信号的持续时间近似于线性操作区域内的抽空控制信号的持续时间。

公开(公告)号：WO1997030357A1

公开(公告)日：1997-08-21

申请号：PCT/SE1997000215

申请日：1997-02-12

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (publ) ,  FRANSSON, Clarence, Jörn, Niklas ,  WILHELMSSON, Mats

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

IPC: G01R25/00

CPC classification number: G01R25/08 ,  G01R23/02 ,  G01R25/005 ,  H03D13/00

Abstract: In accordance with a first aspect of the invention a phase detector for measuring phase differences between K input signals is provided. The phase detector comprises a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. In accordance with a second aspect of the invention, a frequency detector is provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value.

Abstract translation: 根据本发明的第一方面，提供一种用于测量K个输入信号之间的相位差的相位检测器。 相位检测器包括计数器，K个第一寄存器和第一减法器。 每个第一寄存器接收计数器的计数器信号和用于响应于关于输入信号的定时信息来更新计数器值的相应输入信号。 第一个减法器接收计数器值以生成相位差表示值。 根据本发明的第二方面，提供一种频率检测器。 第一个减法器由第二个减法器代替，并包括K个第二个寄存器。 每个第二寄存器连接到相应的第一寄存器。 每个第二寄存器响应于关于输入信号的定时信息，接收其第一寄存器的计数器值和与其第一寄存器相同的输入信号，用于将计数器值备份为备用计数器值。 第二减法器对于每个第二寄存器及其第一寄存器，减去其计数器值以产生频率表示值。

公开(公告)号：WO2017071003A1

公开(公告)日：2017-05-04

申请号：PCT/CN2015/096173

申请日：2015-12-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： GU, Liang ,  CAO, Yuming ,  LEI, Gong ,  DANG, Yen ,  GU, Yifan ,  LEE, Hungyi ,  DESHPANDE, Mamatha ,  SHIH, Shou-Po ,  DUAN, Yan

IPC: H03L7/091

CPC classification number: H03L7/099 ,  H03D13/00 ,  H03K5/135 ,  H03K5/14 ,  H03K19/0948 ,  H03K19/20 ,  H03K2005/00078 ,  H03L7/0807 ,  H03L7/085 ,  H03L7/089 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/033

Abstract: An apparatus, comprising a first sampling circuit configured to sample a clock signal according to a data signal to produce a first sampled signal, a second sampling circuit configured to sample the clock signal according to a delay signal to produce a second sampled signal, and a control circuit coupled to the first sampling circuit and the second sampling circuit, wherein the control circuit is configured to perform a not-and (NAND) operation according to the first sampled signal and the second sampled signal to produce an activation signal for activating a frequency adjustment for the clock signal.

Abstract translation: 一种装置，包括：第一采样电路，被配置为根据数据信号对时钟信号进行采样以产生第一采样信号;第二采样电路，被配置为根据延迟信号对时钟信号进行采样， 产生第二采样信号;以及控制电路，耦合到所述第一采样电路和所述第二采样电路，其中，所述控制电路被配置为根据所述第一采样信号和所述第二采样信号执行不和和（NAND）操作以 产生激活信号以激活时钟信号的频率调整。

公开(公告)号：WO2012152331A1

公开(公告)日：2012-11-15

申请号：PCT/EP2011/057669

申请日：2011-05-12

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL) ,  BAO, Mingquan

Inventor： BAO, Mingquan

IPC: H03L7/093 ,  H03D3/00

CPC classification number: H03L7/093 ,  H03D13/00

Abstract: A phase locked loop (200, 700, 800) with a phase detector (210, 710, 730) whose output signal varies between maximum and minimum points with the phase difference between input signals. A VCO (220, 720, 740) receives the output signal from the phase detector (210, 710, 730) as tuning signal. A first part of the output signal of the VCO (220, 720, 740) is an input signal to the phase detector (210, 710, 730) and a second part is the output signal of the phase locked loop. There is a DC voltage shifter (215, 715, 735) between the phase detector and the VCO, which shifts the DC voltage level of the output signal from the phase detector (210, 710, 730) so that a point at a distance from a centre point between said maximum and minimum points is shifted to zero volts (DC). The phase detector (210, 710, 730) is tunable.

Abstract translation: 具有相位检测器（210,710,730）的锁相环（200,700,800），其输出信号在输入信号之间的相位差在最大和最小点之间变化。 VCO（220,720,740）从相位检测器（210,710,730）接收作为调谐信号的输出信号。 VCO（220,720,740）的输出信号的第一部分是到相位检测器（210,710,730）的输入信号，第二部分是锁相环的输出信号。 在相位检测器和VCO之间存在一个直流电压移位器（215,715,735），它将来自相位检测器（210,710,730）的输出信号的直流电压电平移位，使得距离 所述最大点和最小点之间的中心点移动到零伏特（DC）。 相位检测器（210,710,730）是可调谐的。

公开(公告)号：WO2009041102A1

公开(公告)日：2009-04-02

申请号：PCT/JP2008/057745

申请日：2008-04-22

Applicant: 日本電気株式会社 ,  野口 栄実

Inventor： 野口 栄実

IPC: H03K5/26 ,  H03D13/00 ,  H03L7/085

CPC classification number: H03D13/00 ,  H03K5/135 ,  H03L7/085 ,  H03L7/091

Abstract: 　識別手段は、入力信号をクロック信号のタイミングで識別することにより再生信号を生成し、再生信号を調整可能な位相で出力する。誤差パルス生成手段は、入力信号と識別手段から出力された再生信号との位相差に応じたパルス幅を有する誤差パルス信号を生成する。リファレンスパルス生成手段は、誤差パルス生成手段で生成される誤差パルス信号に対応し、一定のパルス幅を有するリファレンスパルス信号を生成する。差分信号生成手段は、誤差パルス信号とリファレンスパルス信号の差分をとることにより、位相比較の結果を示す位相比較信号を生成する。位相調整手段は、識別手段が再生信号を出力する位相を調整する。

Abstract translation: 识别装置通过用时钟信号的定时识别输入信号来产生再生信号，并以可调节相输出再生信号。 误差脉冲发生装置产生具有对应于从识别装置输出的输入信号和再生信号之间的相位差的脉冲宽度的误差脉冲信号。 基准脉冲发生装置产生与由误差脉冲发生装置产生的具有恒定脉冲宽度的误差脉冲信号相对应的参考脉冲信号。 差分信号发生装置通过取差错脉冲信号和参考脉冲信号之间的差异来产生指示相位比较结果的相位比较信号。 相位调整装置调节识别装置输出再生信号的相位。

公开(公告)号：WO2006071508A3

公开(公告)日：2007-02-22

申请号：PCT/US2005044974

申请日：2005-12-13

Applicant: FREESCALE SEMICONDUCTOR INC ,  JOHNSON TERENCE L ,  MILLER TIMOTHY R

Inventor： JOHNSON TERENCE L ,  MILLER TIMOTHY R

IPC: H03D3/24

CPC classification number: H03L7/093 ,  H03D13/00 ,  H03L7/0991 ,  H04L7/0004 ,  H04L7/033

Abstract: A tracking circuit (100) is provided for controlling a locally-generated clock. A receive channel (110) in the tracking circuit receives an incoming signal and a local clock, generates a local signal based on the local clock, and compares the local signal and the incoming signal to generate a data signal and an unfiltered phase error signal. A loop filter (120) filters the unfiltered phase error signal to provide a filtered phase error signal. A numerically controlled oscillator (140) generates a correction clock based on the filtered phase error signal. And a filter control circuit (160) provides one or more filter control signals to control operational parameters of the loop filter. The correction clock is provided to the receive channel to modify at least one of the phase and frequency of the local clock. In addition, a sample switch (125) may also be provided to sample the unfiltered phase error signal.

Abstract translation: 提供跟踪电路（100）用于控制本地产生的时钟。 跟踪电路中的接收通道（110）接收输入信号和本地时钟，基于本地时钟产生本地信号，并且比较本地信号和输入信号以产生数据信号和未滤波的相位误差信号。 环路滤波器（120）对未滤波的相位误差信号进行滤波以提供滤波的相位误差信号。 数控振荡器（140）基于滤波的相位误差信号产生校正时钟。 并且滤波器控制电路（160）提供一个或多个滤波器控制信号以控制环路滤波器的操作参数。 校正时钟被提供给接收通道以修改本地时钟的相位和频率中的至少一个。 此外，还可以提供采样开关（125）以对未滤波的相位误差信号进行采样。

公开(公告)号：WO2004021574A1

公开(公告)日：2004-03-11

申请号：PCT/IB2003/003726

申请日：2003-07-31

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  VAN DE BEEK, Remco, C., H. ,  KLUMPERINK, Eric, A., M. ,  NAUTA, Bram ,  VAUCHER, Cicero, S.

Inventor： VAN DE BEEK, Remco, C., H. ,  KLUMPERINK, Eric, A., M. ,  NAUTA, Bram ,  VAUCHER, Cicero, S.

IPC: H03L7/089

CPC classification number: H03L7/191 ,  H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/0893 ,  H03L7/113

Abstract: A phase locked loop comprising a phase detector (100) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector (100) comprising: means (10) for obtaining a first one of said frequency control signals (U, D) by binary multiplication of the reference signal (Ref) and one of the relative phase shifted signals (I, Q); and means (20) for obtaining a second one of said frequency control signals (U, D) by binary multiplication of the relative phase shifted signals (I, Q).

Abstract translation: 一种锁相环，包括用于确定参考信号（Ref）和相互相移信号（I，Q）之间的相位差的相位检测器（100），以产生频率控制信号（U，D），相位检测器（100） 包括：用于通过参考信号（Ref）和相对相移信号（I，Q）之一的二进制相乘来获得所述频率控制信号（U，D）中的第一个的装置（10）。 以及用于通过相对相移信号（I，Q）的二进制相乘来获得所述频率控制信号（U，D）中的第二个的装置（20）。

公开(公告)号：WO1985003176A1

公开(公告)日：1985-07-18

申请号：PCT/US1984002133

申请日：1984-12-31

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  LEVINE, Steven, N.

IPC: H03L07/00

CPC classification number: H03D13/00 ,  H03K23/662 ,  H03L7/095 ,  H03L7/0993 ,  H04L7/0331

Abstract: An improved multiple frequency digital phase-locked loop circuit (10). The improved digital phase-locked loops utilizes a single circuit (12) to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal (30) with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The multiple frequency provides frequency adjustments by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controllable clock signal. The improved multifrequency digital phase-locked loop is suitable for use as a tone detector with the addition of the lock detector (22) wherein the phase-locked loop can be programmed for a plurality of known operating frequencies.

Abstract translation: 一种改进的多频数字锁相环电路（10）。 改进的数字锁相环使用单个电路（12）来实现相位和频率调整。 多频数字锁相环通过用导出的可编程时钟信号有选择地组合或减去参考时钟信号（30）来实现相位调整，从而产生复合数字锁相环时钟信号。 多频率通过以可编程可控制的时钟信号确定的速率选择性地从复合时钟信号中增加或减去脉冲来提供频率调节。 改进的多频数字锁相环适合用作附加锁定检测器（22）的音调检测器，其中锁相环可以被编程为多个已知的工作频率。