公开(公告)号：WO2011124630A3

公开(公告)日：2011-12-22

申请号：PCT/EP2011055392

申请日：2011-04-07

Applicant: IBM ,  CIDECIYAN ROY DARON ,  MATSUO HISATO ,  MITTELHOLZER THOMAS ,  OHTANI KENJI ,  SEGER PAUL ,  TANAKA KEISUKE

Inventor： CIDECIYAN ROY DARON ,  MATSUO HISATO ,  MITTELHOLZER THOMAS ,  OHTANI KENJI ,  SEGER PAUL ,  TANAKA KEISUKE

IPC: G11B20/18

CPC classification number: G11B20/18 ,  G11B2020/184 ,  G11B2020/1853 ,  G11B2220/90

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

Abstract translation: 在磁带驱动器中集成数据和标题保护的方法包括接收组织成行和列的数据阵列。 数组被扩展为包含数组中每行数据的一个或多个头。 该方法为阵列中的数据提供纠错码（ECC）保护的两个维度，并为阵列中的头部提供单维度ECC保护。 本文还公开了相应的装置。

公开(公告)号：WO2009060332A3

公开(公告)日：2009-09-11

申请号：PCT/IB2008054372

申请日：2008-10-23

Applicant: IBM ,  MITTELHOLZER THOMAS

Inventor： MITTELHOLZER THOMAS

IPC: H03M7/02

CPC classification number: H03M5/145 ,  H03M7/02 ,  H03M7/3088

Abstract: Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I) -constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.

Abstract translation: 提供了用于对二进制输入数据流进行调制编码的方法和装置。 4进制枚举编码算法被应用于输入比特流以产生一系列4进制输出符号。 4进制算法可用于在输入比特流的奇数和偶数交织中同时编码相应的广义斐波纳契码。 然后每个连续的4进制输出符号的比特被交织，产生具有全局和交织的游程长度约束的输出比特流。 反转四元输出符号的位产生与（G，I）约束的输出比特流，如反向级联调制系统中使用的PRML（G，I）码一样。 还提供了相应的解码系统。