公开(公告)号：WO2018063324A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054778

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SATTIRAJU, Seshu V. ,  GANESAN, Krishna Prakash ,  BHATIA, Ashish ,  SRIRAM, Vinay ,  MUIRHEAD, John ,  KOTHARI, Hiten ,  GUNAWAN, Aloysius A. ,  ARYASOMAYAJULA, Lavanya ,  GOWRISHANKAR, Shravan ,  PATTABHIRAMAN, Sriram ,  GUHA, Sudipto

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

Abstract translation: 包括堆叠的多个IC芯片或管芯并通过焊接电连接的堆叠芯片组件。 根据下面进一步描述的一些实施例，焊料接合将接触包括扩散阻挡层的背侧焊盘以减少金属间形成和/或其他焊料引起的可靠性问题。 背侧焊盘可以包括电解镍（Ni）阻挡层，从背侧再分配层迹线分离焊料。 该电解Ni可以具有高纯度，其至少部分地可以使得背面金属化叠层具有最小的厚度，同时仍然用作扩散阻挡层。 在一些实施例中，背面土地组合物和体系结构不同于正面土地组成和/或体系结构。