公开(公告)号：WO2019125404A1

公开(公告)日：2019-06-27

申请号：PCT/US2017/067227

申请日：2017-12-19

Applicant: INTEL CORPORATION

Inventor： HWANG, Ehren ,  PELTO, Christopher M. ,  SATTIRAJU, Seshu V. ,  GOWRISHANKAR, Shravan ,  ZELL, Zachary A. ,  RAORANE, Digvijay A.

IPC: H01L21/768

Abstract: Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

公开(公告)号：WO2018063405A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055031

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： ZELL, Zachary A. ,  GOWRISHANKAR, Shravan ,  HUSSAIN, A H M Shahadat ,  BURK, Jonathan J. ,  SATTIRAJU, Seshu V.

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/11848 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16221 ,  H01L2224/16507 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Embodiments of the invention include a microelectronic device that includes a layer dielectric material that includes a feature with a depression. A Nickel barrier layer is formed in the depression of the feature and a first conductive layer is formed in the depression of the feature. The microelectronic device can optionally include a second conductive layer formed below the depression of the feature.

Abstract translation: 本发明的实施例包括微电子器件，其包括层介电材料，其包括具有凹陷的特征。 镍阻挡层形成在特征的凹陷中，并且第一导电层形成在特征的凹陷中。 微电子器件可以可选地包括在特征的凹陷下方形成的第二导电层。

公开(公告)号：WO2018063324A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054778

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： SATTIRAJU, Seshu V. ,  GANESAN, Krishna Prakash ,  BHATIA, Ashish ,  SRIRAM, Vinay ,  MUIRHEAD, John ,  KOTHARI, Hiten ,  GUNAWAN, Aloysius A. ,  ARYASOMAYAJULA, Lavanya ,  GOWRISHANKAR, Shravan ,  PATTABHIRAMAN, Sriram ,  GUHA, Sudipto

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/48

Abstract: A stacked-chip assembly including a plurality of IC chips or die that are stacked, and electrically coupled by solder bonds. In accordance with some embodiments described further below, the solder bonds are to contact a back-side land that includes a diffusion barrier to reduce intermetallic formation and/or other solder-induced reliability issues. The back-side land may include an electrolytic nickel (Ni) barrier layer separating solder from a back-side redistribution layer trace. This electrolytic Ni may be of high purity, which at least in part, may enable the backside metallization stack to be of minimal thickness while still functioning as a diffusion barrier. In some embodiments, the back-side land composition and architecture is distinct from a front-side land composition and/or architecture.

Abstract translation: 包括堆叠的多个IC芯片或管芯并通过焊接电连接的堆叠芯片组件。 根据下面进一步描述的一些实施例，焊料接合将接触包括扩散阻挡层的背侧焊盘以减少金属间形成和/或其他焊料引起的可靠性问题。 背侧焊盘可以包括电解镍（Ni）阻挡层，从背侧再分配层迹线分离焊料。 该电解Ni可以具有高纯度，其至少部分地可以使得背面金属化叠层具有最小的厚度，同时仍然用作扩散阻挡层。 在一些实施例中，背面土地组合物和体系结构不同于正面土地组成和/或体系结构。