公开(公告)号：WO2020064231A1

公开(公告)日：2020-04-02

申请号：PCT/EP2019/072483

申请日：2019-08-22

Applicant: INTEL IP CORPORATION ,  INTEL CORPORATION

Inventor： ELLENBECK, Jan ,  ZUKERMAN, Gil ,  BADIC, Biljana ,  MORSY, Karim ,  REICHELMEIR, Thomas Hans-Joerg ,  YANG, Chunyuan ,  GORIS, Norman ,  BRENDEL, Johannes ,  HOFMANN, Christian ,  KIILERICH PRATAS, Nuno Manuel ,  DREWES, Christian

IPC: H04W56/00

Abstract: A wireless device may include a selection processor configured to process selection information to set a duration of a selection period and to start the selection period, a receiver configured to receive a synchronization initiation signal, and a transmitter configured to transmit a synchronization initiation signal after the selection period has expired if the receiver has not received a synchronization initiation signal during the selection period.

公开(公告)号：WO2019067136A1

公开(公告)日：2019-04-04

申请号：PCT/US2018/048210

申请日：2018-08-28

Applicant: INTEL CORPORATION

Inventor： HASHOLZNER, Ralph ,  GORBATOV, Eugene ,  JANIK, Piotr ,  GUPTA, Ajay ,  SINGH, Ashish ,  KOCAGOEZ, Kenan ,  BRENDEL, Johannes ,  MUECK, Markus, Dominik ,  KARLS, Ingolf

IPC: H04W52/02 ,  H04W88/02

CPC classification number: H04W52/228 ,  H04W52/06 ,  H04W52/221 ,  H04W52/223 ,  H04W52/34 ,  H04W52/343 ,  H04W52/346

Abstract: Methods and devices for allocating power among a plurality of circuits in a communication device, including determining a power budget for allocating to the plurality of circuits from a power supply information; receiving an activity status from a first circuit of the plurality of circuits; determining a first power value based on the activity status; deriving a second power value based on the first power value and the power budget; and allocating power to one or more remaining circuits of the plurality of circuits based on the second power value.

公开(公告)号：WO2019066842A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053918

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： MALEVSKY, Sharon ,  GIDONI, Tomer ,  PORAT, Shahar ,  ESHKOLI, Ayal ,  ROMANO, Tom ,  BRENDEL, Johannes ,  MEYER, Stefan

IPC: H03L1/00 ,  G06F1/32 ,  H04W52/02

Abstract: Methods, systems, and circuitries are provided to generate clock signals of different qualities in a device. A method includes determining whether the device is operating in a mid power mode or a high power mode. In response to determining that the device is operating in the mid power mode, oscillator circuitry is controlled to cause the oscillator circuitry to consume a lower amount of power, such that the oscillator circuitry generates a lower quality clock signal. In response to determining that the device is operating in the high power mode, the oscillator circuitry is controlled to cause the oscillator circuitry to consume a higher amount of power, such that the oscillator circuitry generates a higher quality clock signal. The lower amount of power and the higher amount of power are different from one another.