公开(公告)号：WO2021040951A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/043978

申请日：2020-07-29

Applicant: INTEL CORPORATION

Inventor： GUPTA, Praveen Kumar ,  ANANTHAKRISHNAN, Avinash N. ,  GORBATOV, Eugene ,  GUNTHER, Stephen H.

IPC: G06F1/329 ,  G06F1/3237 ,  G06F1/3206 ,  G06F9/50

Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine maximum operating points for the cores based at least in part on the scaled power budget; determine efficiency values for the cores based at least in part on the maximum operating points; and report a hardware state change to an operating system scheduler based on the efficiency values. Other embodiments are described and claimed.

公开(公告)号：WO2018063478A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/043713

申请日：2017-07-25

Applicant: INTEL CORPORATION

Inventor： ABOZAED, Muhammad ,  GORBATOV, Eugene ,  KHANNA, Gaurav ,  ANANTHAKRISHNAN, Avinash N.

IPC: G06F1/32 ,  G06F9/50 ,  G06F15/78

Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

Abstract translation: 实施例通常针对用于支持优先系统事件的增强型功率管理。 系统的实施例包括处理元件; 存储器，其包括用于关于被指定为优先事件的一个或多个系统事件的信息的注册表; 跟踪要求执行Turbo模式操作的事件操作的机制; 和功率控制单元来实现功率管理算法。 该系统将维持第一能量预算和第二剩余能量预算用于在Turbo功率模式下操作，并且其中功率管理算法将基于第二个功率确定是否授权在Turbo功率模式下执行检测到的系统事件 在确定第一能量预算不足以执行检测到的系统事件并且检测到的系统事件被指定为优先事件时，剩余能量预算。 优先级事件的优先级指定可以包括第一个高优先级指定和第二个重要指定。

公开(公告)号：WO2019005461A1

公开(公告)日：2019-01-03

申请号：PCT/US2018/036841

申请日：2018-06-11

Applicant: INTEL CORPORATION

Inventor： NGE, Chee Lim ,  GORBATOV, Eugene ,  WANG, Zhongsheng ,  HERMERDING, II, James G. ,  ASTEKAR, Basavaraj B. ,  CHENG, Jenn Chuan ,  KUO, Chia-Hung Sophia ,  UMAPATHY, Ashwin ,  KUNG, Tin-Cheung ,  LI, Yifan ,  UAN-ZO-LI, Alexander B.

IPC: G06F1/32

Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.

公开(公告)号：WO2018182909A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/020174

申请日：2018-02-28

Applicant: INTEL CORPORATION

Inventor： GORBATOV, Eugene ,  UAN-ZO-LI, Alexander B. ,  ABOZAED, Muhammad ,  ROTEM, Efraim ,  SCHIFF, Tod F. ,  HERMERDING, James, G., II ,  NGE, Chee Lim

IPC: G06F1/32 ,  G06F1/28

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

公开(公告)号：WO2018175030A1

公开(公告)日：2018-09-27

申请号：PCT/US2018/019043

申请日：2018-02-21

Applicant: INTEL CORPORATION

Inventor： UAN-ZO-LI, Alexander B. ,  GORBATOV, Eugene ,  NGE, Chee Lim

IPC: G06F1/32 ,  G08B21/18

Abstract: A method and apparatus for extending peak power capability of a computing device. In one embodiment, the apparatus comprises: voltage monitoring hardware to monitor voltage being supplied by a battery to a system load; and an energy storage coupled to the voltage monitoring hardware and/or charging scheme to supplement supply of power to the system load when the voltage supplied to the system load by the battery, as monitored by the voltage monitoring hardware, drops below a first threshold voltage level, the first threshold voltage level being above a minimum voltage level associated with the computing system.

公开(公告)号：WO2016209487A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/034051

申请日：2016-05-25

Applicant: INTEL CORPORATION

Inventor： VARMA, Ankush ,  FLEMING, Kristoffer D. ,  GORBATOV, Eugene ,  GOUGH, Robert E. ,  SISTLA, Krishnakanth V.

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4893 ,  G06F9/30174 ,  G06F9/455

Abstract: An apparatus and method for performing high performance instruction emulation. For example, one embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-powered instructions if the number of high-power instructions are below the specified threshold.

Abstract translation: 一种用于执行高性能指令仿真的装置和方法。 例如，本发明的一个实施例包括处理包括大功率和标准指令的指令集的处理器，包括：分析模块，用于确定指定窗口内的多个高功率指令是否高于或低于指定阈值; 执行模式选择模块，如果大功率指令的数量高于规定的阈值，则选择大功率指令的本地执行，或者如果大功率指令的数量是大功率指令，则选择高功率指令的仿真执行 低于规定的阈值。

公开(公告)号：WO2014209400A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048778

申请日：2013-06-28

Applicant: INTEL CORPORATION ,  DIEFENBAUGH, Paul S. ,  GORBATOV, Eugene ,  HENROID, Andrew ,  SAMSON, Eric C. ,  COOPER, Barnes

Inventor： DIEFENBAUGH, Paul S. ,  GORBATOV, Eugene ,  HENROID, Andrew ,  SAMSON, Eric C. ,  COOPER, Barnes

IPC: G06F1/26 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。

公开(公告)号：WO2020205154A1

公开(公告)日：2020-10-08

申请号：PCT/US2020/021340

申请日：2020-03-06

Applicant: INTEL CORPORATION

Inventor： UAN-ZO-LI, Alexander B. ,  GORBATOV, Eugene ,  LEHWALDER, Philip R. ,  ZELIKSON, Michael ,  SHEKHAR, Sameer ,  ANGEL, Nimrod ,  DOUGLAS, Jonathan ,  ABOZAED, Muhammad ,  HALLBERG, Alan ,  HUARD, Douglas ,  BURTON, Edward ,  BROWN, Merwin

IPC: G06F1/3296 ,  G05F1/625 ,  G06F1/3206

Abstract: In some examples, a voltage protection apparatus includes a circuit to compare an input voltage of a processor to a threshold voltage, and to provide a throttle signal to the processor if the input voltage of the processor droops below the threshold voltage. The processor input voltage can then be set to a lower voltage and the processor power can thus be lowered.

公开(公告)号：WO2019190685A1

公开(公告)日：2019-10-03

申请号：PCT/US2019/019961

申请日：2019-02-28

Applicant: INTEL CORPORATION

Inventor： SHANBHOGUE, Vedvyas ,  ANANTHAKRISHNAN, Avinash N. ,  GORBATOV, Eugene ,  FENGER, Russell ,  RAJ, Ashok ,  SUBRAMANIAM, Kameswar

IPC: G06F9/445 ,  G06F11/30 ,  G06F11/34

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

公开(公告)号：WO2014105197A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/048352

申请日：2013-06-27

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  SODHI, Inder, M. ,  KHANNA, Gaurv ,  FENGER, Russel, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew D.

IPC: G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3891

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏小型物理处理器核心集。