公开(公告)号：WO2018136123A3

公开(公告)日：2018-07-26

申请号：PCT/US2017/058011

申请日：2017-10-24

Applicant: INTEL CORPORATION

Inventor： BUTERA, William J. ,  STEELY, Simon C., Jr. ,  DISCHLER, Richard J.

IPC: G06F15/173 ,  G06F9/38

Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.

公开(公告)号：WO2018136123A2

公开(公告)日：2018-07-26

申请号：PCT/US2017/058011

申请日：2017-10-24

Applicant: INTEL CORPORATION

Inventor： BUTERA, William J. ,  STEELY, Simon C., Jr. ,  DISCHLER, Richard J.

IPC: G06F15/173 ,  G06F9/38

CPC classification number: G06F15/17381 ,  G06F9/38 ,  G06F9/3897 ,  G06F15/17343

Abstract: Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.