公开(公告)号：WO2020190813A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022851

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： APPU, Abhishek ,  STRIRAMASSARMA, Lakshminarayanan ,  KOKER, Altug ,  COLEMAN, Sean ,  GEORGE, Varghese ,  HUNTER, JR., Arthur ,  INSKO, Brent ,  JANUS, Scott ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0886 ,  G06F12/0862 ,  G06F9/38

Abstract: Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

公开(公告)号：WO2020190808A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022846

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： RAY, Joydeep ,  JANUS, Scott ,  GEORGE, Varghese ,  MAIYURAN, Subramaniam ,  KOKER, Altug ,  APPU, Abhishek ,  SURTI, Prasoonkumar ,  RANGANATHAN, Vasanth ,  ANDREI, Valentin ,  GARG, Ashutosh ,  HAREL, Yoav ,  HUNTER, JR., Arthur ,  KIM, SungYe ,  MACPHERSON, Mike ,  OULD-AHMED-VALL, Elmoustapha ,  SADLER, William ,  STRIRAMASSARMA, Lakshminarayanan ,  VEMULAPALLI, Vikranth

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.