公开(公告)号：WO2022108658A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/051821

申请日：2021-09-23

Applicant: INTEL CORPORATION

Inventor： DALY, Daniel ,  JAIN, Anjali Singhai ,  CHANG, Chih-Jen ,  CHEN, Edmund ,  HATHAWAY, Robert ,  SUNDAR, Naru Dames ,  SZYMANSKI, Pawel ,  MANGAN, John

IPC: H04L12/815 ,  H04L12/935 ,  H04L12/851

Abstract: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS).

公开(公告)号：WO2021050951A1

公开(公告)日：2021-03-18

申请号：PCT/US2020/050506

申请日：2020-09-11

Applicant: INTEL CORPORATION

Inventor： MCDONNELL, Niall ,  EADS, Gage ,  GANGULI, Mrittika ,  HIREMATH, Chetan ,  MANGAN, John ,  PALERMO, Stephen ,  RICHARDSON, Bruce ,  VERPLANKE, Edwin ,  MOSUR, Praveen ,  CHADDICK, Bradley ,  KHADE, Abhishek ,  LAYEK, Abhirupa ,  MAINI, Sarita ,  SHAH, Rahul ,  SHAH, Shrikant ,  BURROUGHS, William ,  SONNIER, David

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50 ,  G06F15/80

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.