公开(公告)号：WO2021050951A1

公开(公告)日：2021-03-18

申请号：PCT/US2020/050506

申请日：2020-09-11

Applicant: INTEL CORPORATION

Inventor： MCDONNELL, Niall ,  EADS, Gage ,  GANGULI, Mrittika ,  HIREMATH, Chetan ,  MANGAN, John ,  PALERMO, Stephen ,  RICHARDSON, Bruce ,  VERPLANKE, Edwin ,  MOSUR, Praveen ,  CHADDICK, Bradley ,  KHADE, Abhishek ,  LAYEK, Abhirupa ,  MAINI, Sarita ,  SHAH, Rahul ,  SHAH, Shrikant ,  BURROUGHS, William ,  SONNIER, David

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/50 ,  G06F15/80

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：WO2017119980A1

公开(公告)日：2017-07-13

申请号：PCT/US2016/065170

申请日：2016-12-06

Applicant: INTEL CORPORATION

Inventor： WANG, Ren ,  WANG, Yipeng ,  HERDRICH, Andrew J. ,  TSAI, Jr-Shian ,  TAI, Tsung-Yuan C. ,  MCDONNELL, Niall D. ,  WILKINSON, Hugh ,  BURRES, Bradley A. ,  RICHARDSON, Bruce ,  VENKATESAN, Namakkal N. ,  BERNSTEIN, Debra ,  VERPLANKE, Edwin ,  VAN DOREN, Stephen R. ,  YAN, An ,  CUNNINGHAM, Andrew ,  SONNIER, David ,  EADS, Gage ,  CLEE, James T. ,  WHITESELL, Jamison D. ,  PIROG, Jerry ,  KENNY, Jonathan ,  HASTING, Joseph R. ,  VANGATI, Narender ,  MILLER, Stephen ,  MA, Te K. ,  BURROUGHS, William

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F13/37 ,  G06F12/0811 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/283

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ("LLC"), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Abstract translation: 实现硬件队列管理设备的装置和方法，用于通过从CPU核卸载请求管理和数据一致性任务来减少核心间数据传输开销。 该设备包括多核处理器，共享的L3或最后一级高速缓存（“LLC”）以及用于接收，存储和处理核心间数据传输请求的硬件队列管理设备。 硬件队列管理设备还包括资源管理系统，用于控制核心可以提交请求以降低核心停顿和丢弃的请求的速率。 此外，还引入了软件指令来优化内核与队列管理设备之间的通信。

公开(公告)号：WO2018125384A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/060432

申请日：2017-11-07

Applicant: INTEL CORPORATION

Inventor： KANTECKI, Tomasz ,  FRIEDMAN, Ben-Zion ,  MCDONNELL, Niall D. ,  RICHARDSON, Bruce

IPC: G06F12/0802

CPC classification number: G06F13/4282 ,  G06F12/0875 ,  G06F13/126 ,  G06F13/4022 ,  G06F2212/452 ,  G06F2213/0026

Abstract: Examples include techniques for coalescing doorbells in a request message. Example techniques include gathering doorbells to access a device. The gathered are combined in a cache line structure and the cache line structure is written to a cache or buffer for a central processing unit in a single write operation.

公开(公告)号：WO2017172217A1

公开(公告)日：2017-10-05

申请号：PCT/US2017/020230

申请日：2017-03-01

Applicant: INTEL CORPORATION

Inventor： WANG, Ren ,  WANG, Yipeng ,  TSAI, Jr-Shian ,  HERDRICH, Andrew J. ,  TAI, Tsung-Yuan C. ,  MCDONNELL, Niall ,  VAN DOREN, Stephen R. ,  SONNIER, David ,  BERNSTEIN, Debra ,  WILKINSON, Hugh ,  VANGATI, Narender ,  MILLER, Stephen ,  EADS, Gage ,  CUNNINGHAM, Andrew ,  KENNY, Jonathan ,  RICHARDSON, Bruce ,  BURROUGHS, William ,  HASTING, Joseph ,  YAN, An ,  CLEE, James ,  MA, Te ,  PIROG, Jerry ,  WHITESELL, Jamison

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F13/36 ,  G06F12/1027 ,  G06F13/24 ,  G06F13/4004 ,  G06F2212/1021 ,  G06F2212/50 ,  G06F2212/68

Abstract: Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

Abstract translation: 分布式硬件队列管理器的技术包括具有处理器的计算设备。 处理器包含两个或更多硬件队列管理器以及两个或更多处理器内核。 每个处理器核心都可以从硬件队列管理器中入队或出队。 每个硬件队列管理器都可以配置为包含多个队列数据结构。 在一些实施例中，处理器内核使用虚拟队列地址寻址队列，所述虚拟队列地址被转换成用于访问相应硬件队列管理器的物理队列地址。 虚拟队列可以从一个硬件队列管理器中的一个物理队列移动到另一个物理队列管理器中的不同物理队列，而不会更改虚拟队列的虚拟地址。