公开(公告)号：WO2023048880A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/041227

申请日：2022-08-23

Applicant: INTEL CORPORATION

Inventor： GRYMEL, Martin-Thomas ,  BERNARD, David ,  POWER, Martin ,  HANRAHAN, Niall ,  BRADY, Kevin

IPC: G06F11/36 ,  G06N3/04 ,  G06F11/277 ,  G06F11/30

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.

公开(公告)号：WO2023048824A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/038710

申请日：2022-07-28

Applicant: INTEL CORPORATION

Inventor： BRADY, Kevin ,  POWER, Martin ,  HANRAHAN, Niall ,  PALLA, Alessandro ,  GRYMEL, Martin-Thomas ,  BERNARD, David

IPC: G06N3/063

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase utilization of neural network (NN) accelerator circuitry for shallow layers of an NN by reformatting one or more tensors. An example apparatus includes parameter determining circuitry to determine a width of a weight kernel and to determine a depth of a first tensor. The example apparatus also includes storage control circuitry to, starting at a first XY location of the first tensor, copy one or more Z values, up to the depth of the first tensor, of consecutive XY locations that overlap the width of the weight kernel and to load the one or more Z values consecutively in a first XY location of a second tensor.

公开(公告)号：WO2023048827A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/038910

申请日：2022-07-29

Applicant: INTEL CORPORATION

Inventor： HANRAHAN, Niall ,  POWER, Martin ,  BRADY, Kevin ,  GRYMEL, Martin-Thomas ,  BERNARD, David ,  BAUGH, Gary ,  BRICK, Cormac

IPC: G06F9/30 ,  G06F7/544 ,  G06F9/38

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that increase data reuse for multiply and accumulate (MAC) operations. An example apparatus includes a MAC circuit to process a first context of a set of a first type of contexts stored in a first buffer and a first context of a set of a second type of contexts stored in a second buffer. The example apparatus also includes control logic circuitry to, in response to determining that there is an additional context of the second type to be processed in the set of the second type of contexts, maintain the first context of the first type in the first buffer. The control logic circuitry is also to, in response to determining that there is an additional context of the first type to be processed in the set of the first type of contexts maintain the first context of the second type in the second buffer and iterate a pointer of the second buffer from a first position to a next position in the second buffer.

公开(公告)号：WO2022271235A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021590

申请日：2022-03-23

Applicant: INTEL CORPORATION

Inventor： POWER, Martin ,  BRADY, Kevin ,  HANRAHAN, Niall ,  GRYMEL, Martin-Thomas ,  BERNARD, David ,  BAUGH, Gary

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/045

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to perform machine-learning model operations on sparse accelerators. An example apparatus includes first circuitry, second circuitry to generate sparsity data based on an acceleration operation, and third circuitry to instruct one or more data buffers to provide at least one of activation data or weight data based on the sparsity data to the first circuitry, the first circuitry to execute the acceleration operation based on the at least one of the activation data or the weight data.