公开(公告)号：WO2021040947A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/043915

申请日：2020-07-28

申请人： INTEL CORPORATION

发明人： SHAMANNA, Gururaj ,  GOYAL, Mitesh ,  SALAKA, Jagadeesh Chandra ,  NAYAK, Purna C. ,  SHARMA, Abhishek ,  SAHU, Harishankar

IPC分类号： H03K3/037 ,  H03K3/012 ,  G06F1/04

摘要： A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing oppurtunities. Swithcing power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.