公开(公告)号：WO2015047276A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/061938

申请日：2013-09-26

Applicant: LURIA, Kosta ,  LYAKHOV, Alexander ,  SHOR, Joseph ,  ZELIKSON, Michael ,  INTEL CORPORATION

Inventor： LURIA, Kosta ,  LYAKHOV, Alexander ,  SHOR, Joseph ,  ZELIKSON, Michael

IPC: G05F1/10 ,  G05B11/01

CPC classification number: G05F1/56 ,  G06F1/266 ,  H02M1/088 ,  H02M2001/0045

Abstract: Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Abstract translation: 描述了一种装置，包括：第一电源节点，用于提供输入电源; 耦合到所述第一电源节点的功率晶体管; 多路复用器，根据功率晶体管是作为低压差稳压器（LDO-VR）的一部分进行功率晶体管的栅极端子选择性地控制还是作为数字开关工作; 以及耦合到所述功率晶体管的第二电源节点，所述第二电源节点向所述功率晶体管的负载提供电力供应。

公开(公告)号：WO2014042726A1

公开(公告)日：2014-03-20

申请号：PCT/US2013/045240

申请日：2013-06-11

Applicant: INTEL CORPORATION

Inventor： PAILLET, Fabrice ,  SHOR, Joseph ,  GEANNOPOULOS, George L. ,  TAN, Hong Yun

IPC: G05F1/10

CPC classification number: G06F1/26 ,  G05F1/56 ,  H03K19/00361

Abstract: Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.

Abstract translation: 描述了一种线性稳压器电路，其包括第一电压调节器，其包括具有第一节点以提供第一电源的第一源极跟随器和与第一节点不同的第二节点; 以及第二电压调节器，其包括具有第一节点以提供第二电源的第二源极跟随器，以及不同于所述第一节点的第二节点，其中所述第一和第二稳压器的第二节点被电短路。

公开(公告)号：WO2016044057A1

公开(公告)日：2016-03-24

申请号：PCT/US2015/049427

申请日：2015-09-10

Applicant: INTEL CORPORATION

Inventor： FAMILIA, Noam ,  SAKSONOV, Avigdor ,  FAYNEH, Eyal ,  SHOR, Joseph

IPC: H03L7/099 ,  H03L7/14

CPC classification number: H03L7/0991 ,  H03B5/10 ,  H03K3/0315 ,  H03L5/00 ,  H03L7/083 ,  H03L7/091 ,  H03L7/093 ,  H03L7/095 ,  H03L7/099 ,  H03L7/0995 ,  H03L7/18

Abstract: Some embodiments include apparatuses and methods having a digitally controlled oscillator (DCO) in a digital phase-locked loop (PLL) and a control loop. The DCO can generate an output signal having a frequency based on a value of a digital information. The control loop can adjust a value of a supply voltage of the DCO based on the value the digital information. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括在数字锁相环（PLL）和控制环路中具有数字控制振荡器（DCO）的装置和方法。 DCO可以产生具有基于数字信息的值的频率的输出信号。 控制回路可以根据数字信息的值调节DCO的电源电压值。 描述附加的装置和方法。

公开(公告)号：WO2015034534A1

公开(公告)日：2015-03-12

申请号：PCT/US2013/058751

申请日：2013-09-09

Applicant: INTEL CORPORATION ,  SHOR, Joseph ,  GEANNOPOULOS, George, L. ,  PAILLET, Fabrice ,  VU, Lan D. ,  DADASHEV, Oleg

Inventor： SHOR, Joseph ,  GEANNOPOULOS, George, L. ,  PAILLET, Fabrice ,  VU, Lan D. ,  DADASHEV, Oleg

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G05F1/575 ,  G05F1/59 ,  G05F3/30 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.

Abstract translation: 描述了一种装置，其包括：带隙芯，用于提供控制信号; 以及耦合到带隙磁芯的输出级，输出级接收控制信号并在输出节点处提供低阻抗输出。

公开(公告)号：WO2013095351A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/065945

申请日：2011-12-19

Applicant: INTEL CORPORATION ,  SHOR, Joseph

Inventor： SHOR, Joseph

IPC: G06F1/26

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3293 ,  G06F1/3296 ,  G06F17/5045 ,  H03K17/302 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: A disable module may be coupled to an analog circuit of an electronic circuit. The disable module may detect an input voltage that is supplied to the analog circuit, and may disable (such as by powering off) the analog circuit if the input voltage is below a reference value. The reference value may be set at a voltage level at or below a maximum voltage that may be present across a transistor in the analog circuit. Accordingly, the analog circuit may be disabled without damage to the transistors of the analog circuit. The disable module may detect whether the input voltage is below the reference value level by comparing the input voltage to a reference voltage. The electronic circuit may include a voltage regulator, and the voltage regulator may include the analog circuit.

Abstract translation: 禁用模块可以耦合到电子电路的模拟电路。 禁用模块可以检测提供给模拟电路的输入电压，并且如果输入电压低于参考值，则可以禁止（例如通过断电）模拟电路。 参考值可以被设置在等于或低于可能存在于模拟电路中的晶体管的最大电压的电压电平。 因此，模拟电路可以被禁用而不损坏模拟电路的晶体管。 禁用模块可以通过将输入电压与参考电压进行比较来检测输入电压是否低于参考值电平。 电子电路可以包括电压调节器，并且电压调节器可以包括模拟电路。